257,351 research outputs found

    A Hardware Time Manager Implementation for the Xenomai Real-Time Kernel of Embedded Linux

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    Nowadays, the use of embedded operating systems in different embedded projects is subject to a tremendous growth. Embedded Linux is becoming one of those most popular EOSs due to its modularity, efficiency, reliability, and cost. One way to make it hard real-time is to include a real-time kernel like Xenomai. One of the key characteristics of a Real-Time Operating System (RTOS) is its ability to meet execution time deadlines deterministically. So, the more precise and flexible the time management can be, the better it can handle efficiently the determinism for different embedded applications. RTOS time precision is characterized by a specific periodic interrupt service controlled by a software time manager. The smaller the period of the interrupt, the better the precision of the RTOS, the more it overloads the CPU, and though reduces the overall efficiency of the RTOS. In this paper, we propose to drastically reduce these overheads by migrating the time management service of Xenomai into a configurable hardware component to relieve the CPU. The hardware component is implemented in a Field Programmable Gate Array coupled to the CPU. This work was achieved in a Master degree project where students could apprehend many fields of embedded systems: RTOS programming, hardware design, performance evaluation, etc.Comment: Embed With Linux (EWiLi) workshop, Lorient : France (2012

    Extension to UML-B Notation and Toolset

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    The UML-B notation has been created as an attempt to combine the success and ease of use of UML, with the verification and rigorous development capabilities of formal methods. However, the notation currently only supports a basic diagram set. To address this we have, in this project, designed and implemented a set of extensions to the UML-B notation that provide a much fuller software engineering experience, critically making UML-B more appealing to industry partners. These extensions comprise five new diagram types, which are aimed at supplying a broader range of design capabilities, such as conceptual Use-Case design and future integration with the ProB animator tool

    On-Line Dependability Enhancement of Multiprocessor SoCs by Resource Management

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    This paper describes a new approach towards dependable design of homogeneous multi-processor SoCs in an example satellite-navigation application. First, the NoC dependability is functionally verified via embedded software. Then the Xentium processor tiles are periodically verified via on-line self-testing techniques, by using a new IIP Dependability Manager. Based on the Dependability Manager results, faulty tiles are electronically excluded and replaced by fault-free spare tiles via on-line resource management. This integrated approach enables fast electronic fault detection/diagnosis and repair, and hence a high system availability. The dependability application runs in parallel with the actual application, resulting in a very dependable system. All parts have been verified by simulation

    System Support for Managing Invalid Bindings

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    Context-aware adaptation is a central aspect of pervasive computing applications, enabling them to adapt and perform tasks based on contextual information. One of the aspects of context-aware adaptation is reconfiguration in which bindings are created between application component and remote services in order to realize new behaviour in response to contextual information. Various research efforts provide reconfiguration support and allow the development of adaptive context-aware applications from high-level specifications, but don't consider failure conditions that might arise during execution of such applications, making bindings between application and remote services invalid. To this end, we propose and implement our design approach to reconfiguration to manage invalid bindings. The development and modification of adaptive context-aware applications is a complex task, and an issue of an invalidity of bindings further complicates development efforts. To reduce the development efforts, our approach provides an application-transparent solution where the issue of the invalidity of bindings is handled by our system, Policy-Based Contextual Reconfiguration and Adaptation (PCRA), not by an application developer. In this paper, we present and describe our approach to managing invalid bindings and compare it with other approaches to this problem. We also provide performance evaluation of our approach

    Uncovering Bugs in Distributed Storage Systems during Testing (not in Production!)

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    Testing distributed systems is challenging due to multiple sources of nondeterminism. Conventional testing techniques, such as unit, integration and stress testing, are ineffective in preventing serious but subtle bugs from reaching production. Formal techniques, such as TLA+, can only verify high-level specifications of systems at the level of logic-based models, and fall short of checking the actual executable code. In this paper, we present a new methodology for testing distributed systems. Our approach applies advanced systematic testing techniques to thoroughly check that the executable code adheres to its high-level specifications, which significantly improves coverage of important system behaviors. Our methodology has been applied to three distributed storage systems in the Microsoft Azure cloud computing platform. In the process, numerous bugs were identified, reproduced, confirmed and fixed. These bugs required a subtle combination of concurrency and failures, making them extremely difficult to find with conventional testing techniques. An important advantage of our approach is that a bug is uncovered in a small setting and witnessed by a full system trace, which dramatically increases the productivity of debugging

    A Low Energy FPGA Platform for Real-Time Event-Based Control

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    We present a wireless sensor node suitable for event-based real-time control networks. The node achieves low-power operation thanks to tight clock synchronisation with the network master (at present we refer to a star network but extensions are envisaged). Also, the node does not employ any programmable device but rather an FPGA, thus being inherently immune to attacks based on code tampering. Experimental results on a simple laboratory apparatus are presented

    A Lightweight and Flexible Mobile Agent Platform Tailored to Management Applications

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    Mobile Agents (MAs) represent a distributed computing technology that promises to address the scalability problems of centralized network management. A critical issue that will affect the wider adoption of MA paradigm in management applications is the development of MA Platforms (MAPs) expressly oriented to distributed management. However, most of available platforms impose considerable burden on network and system resources and also lack of essential functionality. In this paper, we discuss the design considerations and implementation details of a complete MAP research prototype that sufficiently addresses all the aforementioned issues. Our MAP has been implemented in Java and tailored for network and systems management applications.Comment: 7 pages, 5 figures; Proceedings of the 2006 Conference on Mobile Computing and Wireless Communications (MCWC'2006

    Interacting Components

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    SystemCSP is a graphical modeling language based on both CSP and concepts of component-based software development. The component framework of SystemCSP enables specification of both interaction scenarios and relative execution ordering among components. Specification and implementation of interaction among participating components is formalized via the notion of interaction contract. The used approach enables incremental design of execution diagrams by adding restrictions in different interaction diagrams throughout the process of system design. In this way all different diagrams are related into a single formally verifiable system. The concept of reusable formally verifiable interaction contracts is illustrated by designing set of design patterns for typical fault tolerance interaction scenarios
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