Paradigm and Paradox in Topology Control of Power Grids

Corrective Transmission Switching can be used by the grid operator to relieve line overloading and voltage violations, improve system reliability, and reduce system losses. Power grid optimization by means of line switching is typically formulated as a mixed integer programming problem (MIP). Such problems are known to be computationally intractable, and accordingly, a number of heuristic approaches to grid topology reconfiguration have been proposed in the power systems literature. By means of some low order examples (3-bus systems), it is shown that within a reasonably large class of greedy heuristics, none can be found that perform better than the others across all grid topologies. Despite this cautionary tale, statistical evidence based on a large number of simulations using using IEEE 118- bus systems indicates that among three heuristics, a globally greedy heuristic is the most computationally intensive, but has the best chance of reducing generation costs while enforcing N-1 connectivity. It is argued that, among all iterative methods, the locally optimal switches at each stage have a better chance in not only approximating a global optimal solution but also greatly limiting the number of lines that are switched

Paradigm and paradox in topology control of power grids

Corrective Transmission Switching can be used by the grid operator to relieve line overloading and voltage violations, improve system reliability, and reduce system losses. Power grid optimization by means of line switching is typically formulated as a mixed integer programming problem (MIP). Such problems are known to be computationally intractable, and accordingly, a number of heuristic approaches to grid topology reconfiguration have been proposed in the power systems literature. By means of some low order examples (3-bus systems), it is shown that within a reasonably large class of “greedy” heuristics, none can be found that perform better than the others across all grid topologies. Despite this cautionary tale, statistical evidence based on a large number of simulations using IEEE 118-bus systems indicates that among three heuristics, a globally greedy heuristic is the most computationally intensive, but has the best chance of reducing generation costs while enforcing N-1 connectivity. It is argued that, among all iterative methods, the locally optimal switches at each stage have a better chance in not only approximating a global optimal solution but also greatly limiting the number of lines that are switched.First author draf

A Cycle-Based Formulation and Valid Inequalities for DC Power Transmission Problems with Switching

It is well-known that optimizing network topology by switching on and off transmission lines improves the efficiency of power delivery in electrical networks. In fact, the USA Energy Policy Act of 2005 (Section 1223) states that the U.S. should "encourage, as appropriate, the deployment of advanced transmission technologies" including "optimized transmission line configurations". As such, many authors have studied the problem of determining an optimal set of transmission lines to switch off to minimize the cost of meeting a given power demand under the direct current (DC) model of power flow. This problem is known in the literature as the Direct-Current Optimal Transmission Switching Problem (DC-OTS). Most research on DC-OTS has focused on heuristic algorithms for generating quality solutions or on the application of DC-OTS to crucial operational and strategic problems such as contingency correction, real-time dispatch, and transmission expansion. The mathematical theory of the DC-OTS problem is less well-developed. In this work, we formally establish that DC-OTS is NP-Hard, even if the power network is a series-parallel graph with at most one load/demand pair. Inspired by Kirchoff's Voltage Law, we give a cycle-based formulation for DC-OTS, and we use the new formulation to build a cycle-induced relaxation. We characterize the convex hull of the cycle-induced relaxation, and the characterization provides strong valid inequalities that can be used in a cutting-plane approach to solve the DC-OTS. We give details of a practical implementation, and we show promising computational results on standard benchmark instances

A Lower Bound Technique for Communication in BSP

Communication is a major factor determining the performance of algorithms on current computing systems; it is therefore valuable to provide tight lower bounds on the communication complexity of computations. This paper presents a lower bound technique for the communication complexity in the bulk-synchronous parallel (BSP) model of a given class of DAG computations. The derived bound is expressed in terms of the switching potential of a DAG, that is, the number of permutations that the DAG can realize when viewed as a switching network. The proposed technique yields tight lower bounds for the fast Fourier transform (FFT), and for any sorting and permutation network. A stronger bound is also derived for the periodic balanced sorting network, by applying this technique to suitable subnetworks. Finally, we demonstrate that the switching potential captures communication requirements even in computational models different from BSP, such as the I/O model and the LPRAM

Design and Analysis of a Novel Multilevel Single Phase Interconnected H-Bridge Inverter

Inverters allow the use of residential solar power to run household appliances and electronics by converting DC to AC power just like the AC power from the grid. This study looks at the design and implementation of a novel multilevel inverter topology called a single phase interconnected H bridge inverter. By utilizing reduced switching complexity, the multilevel inverter can lower the cost of a typical inverter without sacrificing the power quality. The design is developed and analyzed through simulation and hardware testing to demonstrate a working model. Load testing is performed on the inverter output as well as analysis of a custom filter to optimize the output total harmonic distortion (THD). Results from measurements done in simulation and hardware demonstrate the functionality of the proposed inverter topology, providing quality outputs at no load condition. The thesis will also identify and offer solutions to the problems encountered during the construction and testing of the proposed inverter