176,280 research outputs found
Complex scheduling models and analyses for property-based real-time embedded systems
Modern multi core architectures and parallel applications
pose a significant challenge to the worst-case centric real-time system verification
and design efforts.
The involved model and parameter uncertainty contest the fidelity of formal real-time analyses,
which are mostly based on exact model assumptions.
In this dissertation, various approaches that can accept parameter and model uncertainty
are presented.
In an attempt to improve predictability in worst-case centric analyses, the exploration of timing predictable protocols
are examined for parallel task scheduling on multiprocessors and network-on-chip arbitration.
A novel scheduling algorithm, called stationary rigid gang scheduling, for gang tasks on multiprocessors is proposed.
In regard to fixed-priority wormhole-switched network-on-chips, a more restrictive family of transmission protocols called
simultaneous progression switching protocols is proposed with predictability enhancing properties.
Moreover, hierarchical scheduling for parallel DAG tasks under parameter
uncertainty is studied to achieve temporal- and spatial isolation.
Fault-tolerance as a supplementary reliability aspect of real-time systems
is examined, in spite of dynamic external causes of fault.
Using various job variants, which trade off increased execution time demand with increased error protection,
a state-based policy selection strategy is proposed, which provably assures an acceptable quality-of-service (QoS).
Lastly, the temporal misalignment of sensor data in sensor fusion applications
in cyber-physical systems is examined. A modular analysis based on minimal properties to obtain an upper-bound for the
maximal sensor data time-stamp difference is proposed
Scheduling policies and system software architectures for mixed-criticality computing
Mixed-criticality model of computation is being increasingly
adopted in timing-sensitive systems. The model not only
ensures that the most critical tasks in a system never fails,
but also aims for better systems resource utilization in normal condition. In this report, we describe the widely used
mixed-criticality task model and fixed-priority scheduling
algorithms for the model in uniprocessors. Because of the
necessity by the mixed-criticality task model and scheduling
policies, isolation, both temporal and spatial, among tasks is
one of the main requirements from the system design point
of view. Different virtualization techniques have been used
to design system software architecture with the goal of isolation. We discuss such a few system software architectures
which are being and can be used for mixed-criticality model
of computation
On the tailoring of CAST-32A certification guidance to real COTS multicore architectures
The use of Commercial Off-The-Shelf (COTS) multicores in real-time industry is on the rise due to multicores' potential performance increase and energy reduction. Yet, the unpredictable impact on timing of contention in shared hardware resources challenges certification. Furthermore, most safety certification standards target single-core architectures and do not provide explicit guidance for multicore processors. Recently, however, CAST-32A has been presented providing guidance for software planning, development and verification in multicores. In this paper, from a theoretical level, we provide a detailed review of CAST-32A objectives and the difficulty of reaching them under current COTS multicore design trends; at experimental level, we assess the difficulties of the application of CAST-32A to a real multicore processor, the NXP P4080.This work has been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grant
TIN2015-65316-P and the HiPEAC Network of Excellence.
Jaume Abella has been partially supported by the MINECO under Ramon y Cajal grant RYC-2013-14717.Peer ReviewedPostprint (author's final draft
Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems
In modern Commercial Off-The-Shelf (COTS) multicore systems, each core can
generate many parallel memory requests at a time. The processing of these
parallel requests in the DRAM controller greatly affects the memory
interference delay experienced by running tasks on the platform. In this paper,
we model a modern COTS multicore system which has a nonblocking last-level
cache (LLC) and a DRAM controller that prioritizes reads over writes. To
minimize interference, we focus on LLC and DRAM bank partitioned systems. Based
on the model, we propose an analysis that computes a safe upper bound for the
worst-case memory interference delay. We validated our analysis on a real COTS
multicore platform with a set of carefully designed synthetic benchmarks as
well as SPEC2006 benchmarks. Evaluation results show that our analysis is more
accurately capture the worst-case memory interference delay and provides safer
upper bounds compared to a recently proposed analysis which significantly
under-estimate the delay.Comment: Technical Repor
- …