An Object-oriented Formal Notation: Executable Specifications in Clay = Una notación formal orientada a objetos : especificaciones ejecutables con Clay

This thesis presents Clay, a stateless object-oriented formal notation. Clay is class-based, has a nominal type system that integrates algebraic types and inheritance, has equality, method overriding with Scandinavian semantics, dynamic binding, and a rather permissive overloading. The type system of Clay is used to reject illegal specifications, and also to help guide the translation schemes that define the Clay semantics and the generation of executable prototypes. Clay has a first-order semantics that gives an interpretation in first-order logic of the main object-oriented constructions: inheritance, defining classes by cases, overloading, dynamic binding and static equality. Furthermore, the use of the concrete syntax of an automatic theorem prover (Prover9/Mace4) has allowed mechanising both, the Clay's meta-theory and specifications. For example, some of the theorems about Clay in this thesis have been proved semi-automatically. The thesis presents also a compilation scheme of Clay specifications into Prolog programs. Code can be generated from implicit specifications, even recursive ones, something hard to find in other tools. My implementation takes advantage of various logic programming techniques in order to achieve reasonable efficiency: constraints, constructive negation, Lloyd-Topor transforms, incremental deepening search, etc. A Clay compiler is also contributed, a tool that goes beyond the mathematical presentation of the translations into first-order logic and the synthesis of logic programs. I have built a compiler that supports syntax analysis of modular Clay specifications, type checking, translation of Clay specifications into first-order theories in Prover9/Mace4, and synthesis of executable Prolog prototypes

Perturbation analysis analyzed—mathematical modeling of intact and perturbed gene regulatory circuits for animal development

Gene regulatory networks for animal development are the underlying mechanisms controlling cell fate specification and differentiation. The architecture of gene regulatory circuits determines their information processing properties and their developmental function. It is a major task to derive realistic network models from exceedingly advanced high throughput experimental data. Here we use mathematical modeling to study the dynamics of gene regulatory circuits to advance the ability to infer regulatory connections and logic function from experimental data. This study is guided by experimental methodologies that are commonly used to study gene regulatory networks that control cell fate specification. We study the effect of a perturbation of an input on the level of its downstream genes and compare between the cis-regulatory execution of OR and AND logics. Circuits that initiate gene activation and circuits that lock on the expression of genes are analyzed. The model improves our ability to analyze experimental data and construct from it the network topology. The model also illuminates information processing properties of gene regulatory circuits for animal development

A multi-paradigm language for reactive synthesis

This paper proposes a language for describing reactive synthesis problems that integrates imperative and declarative elements. The semantics is defined in terms of two-player turn-based infinite games with full information. Currently, synthesis tools accept linear temporal logic (LTL) as input, but this description is less structured and does not facilitate the expression of sequential constraints. This motivates the use of a structured programming language to specify synthesis problems. Transition systems and guarded commands serve as imperative constructs, expressed in a syntax based on that of the modeling language Promela. The syntax allows defining which player controls data and control flow, and separating a program into assumptions and guarantees. These notions are necessary for input to game solvers. The integration of imperative and declarative paradigms allows using the paradigm that is most appropriate for expressing each requirement. The declarative part is expressed in the LTL fragment of generalized reactivity(1), which admits efficient synthesis algorithms, extended with past LTL. The implementation translates Promela to input for the Slugs synthesizer and is written in Python. The AMBA AHB bus case study is revisited and synthesized efficiently, identifying the need to reorder binary decision diagrams during strategy construction, in order to prevent the exponential blowup observed in previous work.Comment: In Proceedings SYNT 2015, arXiv:1602.0078

VSS : a VHDL synthesis system

This report describes a register transfer synthesis system that allows a designer to interact with the design process. The designer can modify the compiled design by changing the input description, selecting optimization and mapping strategies, or graphically changing the generated design schematic. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization. The compilation process consists of two phases. First, a design composed of generic components is synthesized from the input description. Second, this design is translated into components from a particular library by a mapper and optimized by a logic optimizer. Redesign to new technologies can be accomplished by changing only the component library