Time-Shared Execution of Realtime Computer Vision Pipelines by Dynamic Partial Reconfiguration

This paper presents an FPGA runtime framework that demonstrates the feasibility of using dynamic partial reconfiguration (DPR) for time-sharing an FPGA by multiple realtime computer vision pipelines. The presented time-sharing runtime framework manages an FPGA fabric that can be round-robin time-shared by different pipelines at the time scale of individual frames. In this new use-case, the challenge is to achieve useful performance despite high reconfiguration time. The paper describes the basic runtime support as well as four optimizations necessary to achieve realtime performance given the limitations of DPR on today's FPGAs. The paper provides a characterization of a working runtime framework prototype on a Xilinx ZC706 development board. The paper also reports the performance of realtime computer vision pipelines when time-shared

Bioresorbable silicon electronics for transient spatiotemporal mapping of electrical activity from the cerebral cortex.

Bioresorbable silicon electronics technology offers unprecedented opportunities to deploy advanced implantable monitoring systems that eliminate risks, cost and discomfort associated with surgical extraction. Applications include postoperative monitoring and transient physiologic recording after percutaneous or minimally invasive placement of vascular, cardiac, orthopaedic, neural or other devices. We present an embodiment of these materials in both passive and actively addressed arrays of bioresorbable silicon electrodes with multiplexing capabilities, which record in vivo electrophysiological signals from the cortical surface and the subgaleal space. The devices detect normal physiologic and epileptiform activity, both in acute and chronic recordings. Comparative studies show sensor performance comparable to standard clinical systems and reduced tissue reactivity relative to conventional clinical electrocorticography (ECoG) electrodes. This technology offers general applicability in neural interfaces, with additional potential utility in treatment of disorders where transient monitoring and modulation of physiologic function, implant integrity and tissue recovery or regeneration are required

An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating

© 2015 IEEE.Leakage power is an important component of the total power consumption in field-programmable gate arrays (FPGAs) built using 90-nm and smaller technology nodes. Power gating was shown to be effective at reducing the leakage power. Previous techniques focus on turning OFF unused FPGA resources at configuration time; the benefit of this approach depends on resource utilization. In this paper, we present an FPGA architecture that enables dynamically controlled power gating, in which FPGA resources can be selectively powered down at run-time. This could lead to significant overall energy savings for applications having modules with long idle times. We also present a CAD flow that can be used to map applications to the proposed architecture. We study the area and power tradeoffs by varying the different FPGA architecture parameters and power gating granularity. The proposed CAD flow is used to map a set of benchmark circuits that have multiple power-gated modules to the proposed architecture. Power savings of up to 83% are achievable for these circuits. Finally, we study a control system of a robot that is used in endoscopy. Using the proposed architecture combined with clock gating results in up to 19% energy savings in this application