26,562 research outputs found
High Quality Compact Delay Test Generation
Delay testing is used to detect timing defects and ensure that a circuit meets its
timing specifications. The growing need for delay testing is a result of the advances in
deep submicron (DSM) semiconductor technology and the increase in clock frequency.
Small delay defects that previously were benign now produce delay faults, due to
reduced timing margins. This research focuses on the development of new test methods
for small delay defects, within the limits of affordable test generation cost and pattern
count.
First, a new dynamic compaction algorithm has been proposed to generate
compacted test sets for K longest paths per gate (KLPG) in combinational circuits or
scan-based sequential circuits. This algorithm uses a greedy approach to compact paths
with non-conflicting necessary assignments together during test generation. Second, to
make this dynamic compaction approach practical for industrial use, a recursive learning
algorithm has been implemented to identify more necessary assignments for each path,
so that the path-to-test-pattern matching using necessary assignments is more accurate.
Third, a realistic low cost fault coverage metric targeting both global and local delay
faults has been developed. The metric suggests the test strategy of generating a different
number of longest paths for each line in the circuit while maintaining high fault coverage.
The number of paths and type of test depends on the timing slack of the paths under this
metric. Experimental results for ISCAS89 benchmark circuits and three industry circuits
show that the pattern count of KLPG can be significantly reduced using the proposed
methods. The pattern count is comparable to that of transition fault test, while achieving
higher test quality. Finally, the proposed ATPG methodology has been applied to an
industrial quad-core microprocessor. FMAX testing has been done on many devices and
silicon data has shown the benefit of KLPG test
Gate Delay Fault Test Generation for Non-Scan Circuits
This article presents a technique for the extension of delay fault test pattern generation to synchronous sequential circuits without making use of scan techniques. The technique relies on the coupling of TDgen, a robust combinational test pattern generator for delay faults, and SEMILET, a sequential test pattern generator for several static fault models. The approach uses a forward propagation-backward justification technique: The test pattern generation is started at the fault location, and after successful ¿local¿ test generation fault effect propagation is performed and finally a synchronising sequence to the required state is computed. The algorithm is complete for a robust gate delay fault model, which means that for every testable fault a test will be generated, assuming sufficient time. Experimental results for the ISCAS'89 benchmarks are presented in this pape
LOT: Logic Optimization with Testability - new transformations for logic synthesis
A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed–Muller expansions have been introduced in the synthesis of multilevel circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology not only can achieve lower area than other similar tools, but that it achieves better testability compared to available testability enhancement tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations successfully contributed toward generating smaller circuits compared to other state-of-the-art logic optimization tools
Online Fault Classification in HPC Systems through Machine Learning
As High-Performance Computing (HPC) systems strive towards the exascale goal,
studies suggest that they will experience excessive failure rates. For this
reason, detecting and classifying faults in HPC systems as they occur and
initiating corrective actions before they can transform into failures will be
essential for continued operation. In this paper, we propose a fault
classification method for HPC systems based on machine learning that has been
designed specifically to operate with live streamed data. We cast the problem
and its solution within realistic operating constraints of online use. Our
results show that almost perfect classification accuracy can be reached for
different fault types with low computational overhead and minimal delay. We
have based our study on a local dataset, which we make publicly available, that
was acquired by injecting faults to an in-house experimental HPC system.Comment: Accepted for publication at the Euro-Par 2019 conferenc
Efficient Path Delay Test Generation with Boolean Satisfiability
This dissertation focuses on improving the accuracy and efficiency of path delay test generation using a Boolean satisfiability (SAT) solver. As part of this research, one of the most commonly used SAT solvers, MiniSat, was integrated into the path delay test generator CodGen. A mixed structural-functional approach was implemented in CodGen where longest paths were detected using the K Longest Path Per Gate (KLPG) algorithm and path justification and dynamic compaction were handled with the SAT solver.
Advanced techniques were implemented in CodGen to further speed up the performance of SAT based path delay test generation using the knowledge of the circuit structure. SAT solvers are inherently circuit structure unaware, and significant speedup can be availed if structure information of the circuit is provided to the SAT solver. The advanced techniques explored include: Dynamic SAT Solving (DSS), Circuit Observability Don’t Care (Cir-ODC), SAT based static learning, dynamic learnt clause management and Approximate Observability Don’t Care (ACODC). Both ISCAS 89 and ITC 99 benchmarks as well as industrial circuits were used to demonstrate that the performance of CodGen was significantly improved with MiniSat and the use of circuit structure
GRASP: A New Search Algorithm for Satisfiability
This paper introduces GRASP (Generic search Algorithm J3r the Satisfiabilily Problem), an integrated algorithmic J3amework 30r SAT that unifies several previously proposed searchpruning techniques and jcilitates identification of additional ones. GRASP is premised on the inevitability of conflicts during search and its most distinguishingjature is the augmentation of basic backtracking search with a powerful conflict analysis procedure. Analyzing conflicts to determine their causes enables GRASP to backtrack non-chronologically to earlier levels in the search tree, potentially pruning large portions of the search space. In addition, by 'ecording" the causes of conflicts, GRASP can recognize and preempt the occurrence of similar conflicts later on in the search. Einally, straighrward bookkeeping of the causali y chains leading up to conflicts a/lows GRASP to identij) assignments that are necessary jr a solution to be found. Experimental results obtained jom a large number of benchmarks, including many J3om the field of test pattern generation, indicate that application of the proposed conflict analysis techniques to SAT algorithms can be extremely ejctive jr a large number of representative classes of SAT instances
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