6 research outputs found

    Intermittent resistive faults in digital cmos circuits

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    A major threat in extremely dependable high-end process node integrated systems in e.g. Avionics are no failures found (NFF). One category of NFFs is the intermittent resistive fault, often originating from bad (e.g. Via or TSV-based) interconnections. This paper will show the impact of these faults on the behavior of a digital CMOS circuit via simulation. As the occurrence rate of this kind of defects can take e.g. One month, while the duration of the defect can be as short as 50 nanoseconds, to evoke and detect these faults is a huge scientific challenge. An on-chip data logging system with time stamp and stored environmental conditions, along with the detection, will drastically improve the task of maintenance of avionics and reduce the current high debugging costs

    Temperature-Gradient-Based Burn-In and Test Scheduling for 3-D Stacked ICs

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    Large temperature gradients exacerbate various types of defects including early-life failures and delay faults. Efficient detection of these defects requires that burn-in and test for delay faults, respectively, are performed when temperature gradients with proper magnitudes are enforced on an Integrated Circuit (IC). This issue is much more important for 3-D stacked ICs (3-D SICs) compared with 2-D ICs because of the larger temperature gradients in 3-D SICs. In this paper, two methods to efficiently enforce the specified temperature gradients on the IC, for burn-in and delay-fault test, are proposed. The specified temperature gradients are enforced by applying high-power stimuli to the cores of the IC under test through the test access mechanism. Therefore, no external heating mechanism is required. The tests, high power stimuli, and cooling intervals are scheduled together based on temperature simulations so that the desired temperature gradients are rapidly enforced. The schedule generation is guided by functions derived from a set of thermal equations. The experimental results demonstrate the efficiency of the proposed methods

    Temperature-Gradient-Based Burn-In and Test Scheduling for 3-D Stacked ICs

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    Thermal Issues in Testing of Advanced Systems on Chip

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    Theoretical and Computational Research in Various Scheduling Models

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    Nine manuscripts were published in this Special Issue on “Theoretical and Computational Research in Various Scheduling Models, 2021” of the MDPI Mathematics journal, covering a wide range of topics connected to the theory and applications of various scheduling models and their extensions/generalizations. These topics include a road network maintenance project, cost reduction of the subcontracted resources, a variant of the relocation problem, a network of activities with generally distributed durations through a Markov chain, idea on how to improve the return loading rate problem by integrating the sub-tour reversal approach with the method of the theory of constraints, an extended solution method for optimizing the bi-objective no-idle permutation flowshop scheduling problem, the burn-in (B/I) procedure, the Pareto-scheduling problem with two competing agents, and three preemptive Pareto-scheduling problems with two competing agents, among others. We hope that the book will be of interest to those working in the area of various scheduling problems and provide a bridge to facilitate the interaction between researchers and practitioners in scheduling questions. Although discrete mathematics is a common method to solve scheduling problems, the further development of this method is limited due to the lack of general principles, which poses a major challenge in this research field
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