A 1.2-V 10- µW NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2 °C (3σ) From 70 °C to 125 °C

An NPN-based temperature sensor with digital output transistors has been realized in a 65-nm CMOS process. It achieves a batch-calibrated inaccuracy of ±0.5 ◦C (3¾) and a trimmed inaccuracy of ±0.2 ◦C (3¾) over the temperature range from −70 ◦C to 125 ◦C. This performance is obtained by the use of NPN transistors as sensing elements, the use of dynamic techniques, i.e. correlated double sampling and dynamic element matching, and a single room-temperature trim. The sensor draws 8.3 μA from a 1.2-V supply and occupies an area of 0.1 mm2

Modeling the Temperature Bias of Power Consumption for Nanometer-Scale CPUs in Application Processors

We introduce and experimentally validate a new macro-level model of the CPU temperature/power relationship within nanometer-scale application processors or system-on-chips. By adopting a holistic view, this model is able to take into account many of the physical effects that occur within such systems. Together with two algorithms described in the paper, our results can be used, for instance by engineers designing power or thermal management units, to cancel the temperature-induced bias on power measurements. This will help them gather temperature-neutral power data while running multiple instance of their benchmarks. Also power requirements and system failure rates can be decreased by controlling the CPU's thermal behavior. Even though it is usually assumed that the temperature/power relationship is exponentially related, there is however a lack of publicly available physical temperature/power measurements to back up this assumption, something our paper corrects. Via measurements on two pertinent platforms sporting nanometer-scale application processors, we show that the power/temperature relationship is indeed very likely exponential over a 20{\deg}C to 85{\deg}C temperature range. Our data suggest that, for application processors operating between 20{\deg}C and 50{\deg}C, a quadratic model is still accurate and a linear approximation is acceptable.Comment: Submitted to SAMOS 2014; International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV

Differential temperature sensors: Review of applications in the test and characterization of circuits, usage and design methodology

Differential temperature sensors can be placed in integrated circuits to extract a signature ofthe power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper firstdiscusses the singularity that differential temperature sensors provide with respect to other sensortopologies, with circuit monitoring being their main application. The paper focuses on the monitoringof radio-frequency analog circuits. The strategies to extract the power signature of the monitoredcircuit are reviewed, and a list of application examples in the domain of test and characterizationis provided. As a practical example, we elaborate the design methodology to conceive, step bystep, a differential temperature sensor to monitor the aging degradation in a class-A linear poweramplifier working in the 2.4 GHz Industrial Scientific Medical—ISM—band. It is discussed how,for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamicrange is required. A circuit solution for this objective is proposed, as well as recommendations for thedimensions and location of the devices that form the temperature sensor. The paper concludes with adescription of a simple procedure to monitor time variability.Postprint (published version

Sensor de temperatura CMOS integrado

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-Graduação em Engenharia ElétricaEste trabalho apresenta um sensor de temperatura CMOS integrado voltado ao monitoramento de hot-spots em circuitos VLSI. Seu funcionamento é baseado no comportamento CTAT (complementar a temperatura absoluta) da tensão de limiar do transistor MOS. Devido a este fato, inicia-se a dissertação apresentando alguns métodos utilizados na extração deste parâmetro através de simulações. Em seguida, medições realizadas em alguns transistores de teste servem para validar os resultados obtidos nas simulações. O projeto do sensor é, então, apresentado detalhando-se seus blocos constituintes separadamente: gerador de corrente específica, comparador e gerador do pulso de saída. Em todos os blocos tomou-se o cuidado para que o consumo total do sensor fosse na ordem de poucas dezenas de microwatts de modo a possibilitar o instanciamento de diversos elementos para o mapeamento térmico de um microprocessador. O gerador de corrente específica foi utilizado para fornecer tanto uma corrente quanto uma tensão de referência. A simulação do sensor completo apresentou um consumo de 18mW no pior caso a 120°C. A área total do sensor foi de 0,006mm² em uma tecnologia de 0,18µm. Medições de três amostras do protótipo fabricado demonstraram que a corrente apresentou discrepância de aproximadamente 5% de chip para chip e, no pior caso, variação de 4% na faixa de 0°C a 100°C. Uma variação máxima de chip para chip de 13mV, a 20°C, foi medida na tensão de referência, apresentando todas as amostras uma faixa dinâmica de 170mV de 0°C a 100°C, com um erro médio máximo na linearidade com respeito à temperatura de 1,87°C na faixa de 20°C a 100°C.This work presents a CMOS integrated temperature sensor aiming at monitoring hot-spots in microprocessors. Its principle is based on the CTAT dependance of the threshold voltage of the MOS transistor. Therefore, we start showing some threshold voltage extraction procedures with their results being validated through measurements in test transistors. The design of the main sesnsor blocks, namely, specific currente generator, comparator and pulse generator is presented. The total sensor power consumption was kept close to a few of tens of microwatts in order to allow the placement of various sensor elements in a microprocessor. The specific current generator provides both current and voltage references. The simulation indicated a power consumption of 18mW in the worst case at 120°C. The total area was 0.006mm2 in a 0.18um technology. Measurements on three samples showed a chip-to-chip variation around 5% for the reference current and, in the worst case, 4% variation from 0°C to 100°C. The reference voltage presented maximum 13mV at 20°C variation for chip-to-chip and, for 3 samples, a variation around 170mV from 0°C to 100°C and a maximum average linearity error equals to 1.87°C in 20°C to 100°C range

DVS-capable ultra-low-power subthreshold CMOS temperature sensor / by Gregory Toombs.

There are many contemporary contexts in which a small, low-power-consumption temperature sensor is very valuable. Power, area, speed and temperature range factors are important constraints in modern VLSI design. As transistor dimensions decrease, it is possible to lower the operating voltage of circuits, and dynamic voltage scaling (DVS) has been successfully implemented in several commercial applications to reduce power consumption. Power density is increasing, and the resultant temperature issues are being addressed by DVS, considered an efficient dynamic thermal management (DTM) technique. DVS/DTM automation techniques require thermal sensors that operate over a range of supply voltages. Therefore, temperature sensor designs such as this one are needed to address these engineering challenges. In this thesis, a DVS-capable ultra-low-power sub threshold temperature sensor in 180 nm CMOS technology is proposed. The design is composed of a proportional-to-absolute-temperature (PTAT) current generator modified for insensitivity to power supply variation. The design is monolithic; the included reference current generator is a peaking source whose input is fed back from the output of the sensor. The design procedure includes empirical parameter extraction from BSIM simulations to yield a transistor model viable for design calculations, and adjustments to biasing and transistor dimensions to minimize power consumption and maintain adequate voltage supply independence and linearity. The design utilizes the exponential characteristics of sub threshold CMOS transistors to construct an output current that is a firstorder Taylor approximation proportional to the thermal voltage. This is the first time such a design scheme is presented

Integrated temperature sensors in deep sub-micron CMOS technologies

textIntegrated temperature sensors play an important role in enhancing the performance of on-chip power and thermal management systems in today's highly-integrated system-on-chip (SoC) platforms, such as microprocessors. Accurate on-chip temperature measurement is essential to maximize the performance and reliability of these SoCs. However, due to non-uniform power consumption by different functional blocks, microprocessors have fairly large thermal gradient (and variation) across their chips. In the case of multi-core microprocessors for example, there are task-specific thermal gradients across different cores on the same die. As a result, multiple temperature sensors are needed to measure the temperature profile at all relevant coordinates of the chip. Subsequently, the results of the temperature measurements are used to take corrective measures to enhance the performance, or save the SoC from catastrophic over-heating situations which can cause permanent damage. Furthermore, in a large multi-core microprocessor, it is also imperative to continuously monitor potential hot-spots that are prone to thermal runaway. The locations of such hot spots depend on the operations and instruction the processor carries out at a given time. Due to practical limitations, it is an overkill to place a big size temperature sensor nearest to all possible hot spots. Thus, an ideal on-chip temperature sensor should have minimal area so that it can be placed non-invasively across the chip without drastically changing the chip floor plan. In addition, the power consumption of the sensors should be very low to reduce the power budget overhead of thermal monitoring system, and to minimize measurement inaccuracies due to self-heating. The objective of this research is to design an ultra-small size and ultra-low power temperature sensor such that it can be placed in the intimate proximity of all possible hot spots across the chip. The general idea is to use the leakage current of a reverse-bias p-n junction diode as an operand for temperature sensing. The tasks within this project are to examine the theoretical aspect of such sensors in both Silicon-On-Insulator (SOI), and bulk Complementary Metal-Oxide Semiconductor (CMOS) technologies, implement them in deep sub-micron technologies, and ultimately evaluate their performances, and compare them to existing solutions.Electrical and Computer Engineerin

NEGATIVE BIAS TEMPERATURE INSTABILITY STUDIES FOR ANALOG SOC CIRCUITS

Negative Bias Temperature Instability (NBTI) is one of the recent reliability issues in sub threshold CMOS circuits. NBTI effect on analog circuits, which require matched device pairs and mismatches, will cause circuit failure. This work is to assess the NBTI effect considering the voltage and the temperature variations. It also provides a working knowledge of NBTI awareness to the circuit design community for reliable design of the SOC analog circuit. There have been numerous studies to date on the NBTI effect to analog circuits. However, other researchers did not study the implication of NBTI stress on analog circuits utilizing bandgap reference circuit. The reliability performance of all matched pair circuits, particularly the bandgap reference, is at the mercy of aging differential. Reliability simulation is mandatory to obtain realistic risk evaluation for circuit design reliability qualification. It is applicable to all circuit aging problems covering both analog and digital. Failure rate varies as a function of voltage and temperature. It is shown that PMOS is the reliabilitysusceptible device and NBTI is the most vital failure mechanism for analog circuit in sub-micrometer CMOS technology. This study provides a complete reliability simulation analysis of the on-die Thermal Sensor and the Digital Analog Converter (DAC) circuits and analyzes the effect of NBTI using reliability simulation tool. In order to check out the robustness of the NBTI-induced SOC circuit design, a bum-in experiment was conducted on the DAC circuits. The NBTI degradation observed in the reliability simulation analysis has given a clue that under a severe stress condition, a massive voltage threshold mismatch of beyond the 2mV limit was recorded. Bum-in experimental result on DAC proves the reliability sensitivity of NBTI to the DAC circuitry