Arquitetura de tempo discreto para receptor de radiofrequência baseada em subamostragem com baixa frequencia intermediária e dupla quadratura

Orientador : Prof. Dr. Luis Henrique A. LolisDissertação (mestrado) - Universidade Federal do Paraná, Setor de Tecnologia, Programa de Pós-Graduação em Engenharia Elétrica. Defesa: Curitiba, 17/08/2017Inclui referências : f. 74-77Resumo: Neste trabalho, é apresentada uma arquitetura para receptor baseada em subamostragem, explorando uma baixa frequencia intermediaria, implementando a demodulacao do sinal e rejeicao de sinal imagem sem o uso de osciladores de frequencia variavel. O trabalho iniciou com um estudo do estado-da-arte de arquiteturas de receptores de radiofrequencia baseados em tempo discreto, as quais foram classificadas em duas famílias. Analisando as características mais atraentes de tais arquiteturas, um novo sistema foi proposto. Um estudo de revisao bibliografica foi realizado para compreender os conceitos envolvidos no trabalho. Nesta nova arquitetura, o sinal em radiofrequencia (RF) e deslocado para uma frequencia intermediaria baixa com subamostragem em dupla quadratura. Uma frequencia de amostragem fixa e reduzida e utilizada. O segundo deslocamento em frequencia em quadratura e obtido com o uso de amplificadores com ganho variavel programaveis, o que e feito no tempo discreto ao multiplicar o sinal amostrado com o formato de ondas discretas do seno e cosseno na frequencia intermediaria (IF). O conceito de multibanda pode ser explorado ao escolher harmônicas diferentes do sinal de amostragem para fazer o primeiro deslocamento em frequencia do sinal. Atraves do dimensionamento sistemico e da definicao do plano de frequencia, a arquitetura mostrou-se apropriada para os padroes LTE e IEEE802.11g. O sistema foi modelado usando a ferramenta ADS Ptolemy e validado ao demodular corretamente os sinais nos padroes acima citados para os testes de sensibilidade e de nao linearidade usando o ponto de intersecao de terceira ordem. A rejeicao de imagem obtida para esta arquitetura foi de 46 dB usando uma configuracao de 6 bits. Palavras chave: subamostragem, receptor RF, low-IF, rejeicao de imagem.Abstract: This work presents a bandpass sampling receiver architecture, with a low IF approach while implementing downconversion and image rejection without mixer or frequencyvarying oscillators. The work starts with a study of the state-of-art discrete time receiver architectures, which have been separated in two types of families of systems. After identifying the most attractive features of each architecture, a new system was proposed. A theoretical study about communication fundamentals was made to support this work. In the proposed architecture, the RF signal is downcoverted to a low-IF by means of a quadrature bandpass sampling. A fixed and reduced sampling frequency is applied. The second quadrature downconversion to baseband is accomplished using time-varying gain amplifiers, which is done in discrete time domain by multiplying the signal with discrete cosine and sine waves of the IF. Multiband can be addressed by choosing a different harmonic of the sampling signal to shift the signal frequency. The system level budget carried along the frequency plan showed the suitability of such receiver for the LTE and IEEE802.11g standards. The system was modelled using ADS Ptolemy and validated while correctly downconverting and demodulating the IEEE802.11g and LTE signals for the sensitivity and non-linearity tests. The obtained image rejection of the architecture for 6 bits was 46 dB. Key-words: Bandpass sampling, RF receiver, low-IF, image rejectio

Receiver Front-Ends in CMOS with Ultra-Low Power Consumption

Historically, research on radio communication has focused on improving range and data rate. In the last decade, however, there has been an increasing demand for low power and low cost radios that can provide connectivity with small devices around us. They should be able to offer basic connectivity with a power consumption low enough to function extended periods of time on a single battery charge, or even energy scavenged from the surroundings. This work is focused on the design of ultra-low power receiver front-ends intended for a receiver operating in the 2.4GHz ISM band, having an active power consumption of 1mW and chip area of 1mm². Low power consumption and small size make it hard to achieve good sensitivity and tolerance to interference. This thesis starts with an introduction to the overall receiver specifications, low power radio and radio standards, front-end and LO generation architectures and building blocks, followed by the four included papers. Paper I demonstrates an inductorless front-end operating at 915MHz, including a frequency divider for quadrature LO generation. An LO generator operating at 2.4GHz is shown in Paper II, enabling a front-end operating above 2GHz. Papers III and IV contain circuits with combined front-end and LO generator operating at or above the full 2.45GHz target frequency. They use VCO and frequency divider topologies that offer efficient operation and low quadrature error. An efficient passive-mixer design with improved suppression of interference, enables an LNA-less design in Paper IV capable of operating without a SAW-filter

System Design of Bandpass Sampling RF Receivers

International audienceThis paper presents a novel method for analyzing the analog specifications of bandpass sampling (BPS) receivers. The method guarantees fast convergence to the required performance and can be exploited to study the best configurations for a given constraint (eg. power, integration) using different noise degradation distributions. A wide-band system-level simulation tool which separately models each degradation source is developed to validate the method