569 research outputs found
Synthetic retina for AER systems development
Neuromorphic engineering tries to mimic biology in
information processing. Address-Event Representation (AER) is
a neuromorphic communication protocol for spiking neurons
between different layers. AER bio-inspired image sensor are
called “retina”. This kind of sensors measure visual information
not based on frames from real life and generates corresponding
events. In this paper we provide an alternative, based on cheap
FPGA, to this image sensors that takes images provided by an
analog video source (video composite signal), digitalizes it and
generates AER streams for testing purposes.Junta de Andalucía P06-TIC-01417Ministerio de Educación y Ciencia TEC2006-11730-C03-0
From Vision Sensor to Actuators, Spike Based Robot Control through Address-Event-Representation
One field of the neuroscience is the neuroinformatic whose aim is to
develop auto-reconfigurable systems that mimic the human body and brain. In
this paper we present a neuro-inspired spike based mobile robot. From
commercial cheap vision sensors converted into spike information, through
spike filtering for object recognition, to spike based motor control models. A
two wheel mobile robot powered by DC motors can be autonomously
controlled to follow a line drown in the floor. This spike system has been
developed around the well-known Address-Event-Representation mechanism to
communicate the different neuro-inspired layers of the system. RTC lab has
developed all the components presented in this work, from the vision sensor, to
the robot platform and the FPGA based platforms for AER processing.Ministerio de Ciencia e Innovación TEC2006-11730-C03-02Junta de Andalucía P06-TIC-0141
Real-time motor rotation frequency detection with event-based visual and spike-based auditory AER sensory integration for FPGA
Multisensory integration is commonly
used in various robotic areas to collect more
environmental information using different and
complementary types of sensors. Neuromorphic
engineers mimics biological systems behavior to
improve systems performance in solving engineering
problems with low power consumption. This work
presents a neuromorphic sensory integration scenario
for measuring the rotation frequency of a motor using
an AER DVS128 retina chip (Dynamic Vision Sensor)
and a stereo auditory system on a FPGA completely
event-based. Both of them transmit information with
Address-Event-Representation (AER). This
integration system uses a new AER monitor hardware
interface, based on a Spartan-6 FPGA that allows two
operational modes: real-time (up to 5 Mevps through
USB2.0) and data logger mode (up to 20Mevps for
33.5Mev stored in onboard DDR RAM). The sensory
integration allows reducing prediction error of the
rotation speed of the motor since audio processing
offers a concrete range of rpm, while DVS can be
much more accurate.Ministerio de Economía y Competitividad TEC2012-37868-C04-02/0
Building Blocks for Spikes Signals Processing
Neuromorphic engineers study models and
implementations of systems that mimic neurons behavior in the
brain. Neuro-inspired systems commonly use spikes to
represent information. This representation has several
advantages: its robustness to noise thanks to repetition, its
continuous and analog information representation using digital
pulses, its capacity of pre-processing during transmission time,
... , Furthermore, spikes is an efficient way, found by nature, to
codify, transmit and process information. In this paper we
propose, design, and analyze neuro-inspired building blocks
that can perform spike-based analog filters used in signal
processing. We present a VHDL implementation for FPGA.
Presented building blocks take advantages of the spike rate
coded representation to perform a massively parallel processing
without complex hardware units, like floating point arithmetic
units, or a large memory. Those low requirements of hardware
allow the integration of a high number of blocks inside a FPGA,
allowing to process fully in parallel several spikes coded signals.Junta de Andalucía P06-TIC-O1417Ministerio de Ciencia e Innovación TEC2009-10639-C04-02Ministerio de Ciencia e Innovación TEC2006-11730-C03-0
Embedding Multi-Task Address-Event- Representation Computation
Address-Event-Representation, AER, is a communication protocol that is
intended to transfer neuronal spikes between bioinspired chips. There are
several AER tools to help to develop and test AER based systems, which may
consist of a hierarchical structure with several chips that transmit spikes
among them in real-time, while performing some processing. Although these
tools reach very high bandwidth at the AER communication level, they require
the use of a personal computer to allow the higher level processing of the
event information. We propose the use of an embedded platform based on a
multi-task operating system to allow both, the AER communication and
processing without the requirement of either a laptop or a computer. In this
paper, we present and study the performance of an embedded multi-task AER
tool, connecting and programming it for processing Address-Event
information from a spiking generator.Ministerio de Ciencia e Innovación TEC2006-11730-C03-0
A spatial contrast retina with on-chip calibration for neuromorphic spike-based AER vision systems
We present a 32 32 pixels contrast retina microchip that provides its output as an address event representation (AER) stream. Spatial contrast is computed as the ratio between pixel photocurrent and a local average between neighboring pixels obtained with a diffuser network. This current-based computation produces an important amount of mismatch between neighboring pixels, because the currents can be as low as a few pico-amperes. Consequently, a compact calibration circuitry has been included to trimm each pixel. Measurements show a reduction in mismatch standard deviation from 57% to 6.6% (indoor light). The paper describes the design of the pixel with its spatial contrast computation and calibration sections. About one third of pixel area is used for a 5-bit calibration circuit. Area of pixel is 58 m 56 m, while its current consumption is about 20 nA at 1-kHz event rate. Extensive experimental results are provided for a prototype fabricated in a standard 0.35- m CMOS process.Gobierno de España TIC2003-08164-C03-01, TEC2006-11730-C03-01European Union IST-2001-3412
AER tools for Communications and Debugging
Address-event-representation (AER) is a communications protocol for transferring spikes between bio-inspired chips. Such systems may consist of a hierarchical structure with several chips that transmit spikes among them in real time, while performing some processing. To develop and test AER based systems it is convenient to have a set of instruments that would allow to: generate AER streams, monitor the output produced by neural chips and modify the spike stream produced by an emitting chip to adapt it to the requirements of the receiving elements. In this paper we present a set of tools that implement these functions developed in the CAVIAR EU projectUnión Europea IST-2001-34124 (CAVIAR)Ministerio de Ciencia y Tecnología TIC-2003-08164-C03-0
Real time unsupervised learning of visual stimuli in neuromorphic VLSI systems
Neuromorphic chips embody computational principles operating in the nervous
system, into microelectronic devices. In this domain it is important to
identify computational primitives that theory and experiments suggest as
generic and reusable cognitive elements. One such element is provided by
attractor dynamics in recurrent networks. Point attractors are equilibrium
states of the dynamics (up to fluctuations), determined by the synaptic
structure of the network; a `basin' of attraction comprises all initial states
leading to a given attractor upon relaxation, hence making attractor dynamics
suitable to implement robust associative memory. The initial network state is
dictated by the stimulus, and relaxation to the attractor state implements the
retrieval of the corresponding memorized prototypical pattern. In a previous
work we demonstrated that a neuromorphic recurrent network of spiking neurons
and suitably chosen, fixed synapses supports attractor dynamics. Here we focus
on learning: activating on-chip synaptic plasticity and using a theory-driven
strategy for choosing network parameters, we show that autonomous learning,
following repeated presentation of simple visual stimuli, shapes a synaptic
connectivity supporting stimulus-selective attractors. Associative memory
develops on chip as the result of the coupled stimulus-driven neural activity
and ensuing synaptic dynamics, with no artificial separation between learning
and retrieval phases.Comment: submitted to Scientific Repor
On the AER Stereo-Vision Processing: A Spike Approach to Epipolar Matching
Image processing in digital computer systems usually considers
visual information as a sequence of frames. These frames are from cameras that
capture reality for a short period of time. They are renewed and transmitted at a
rate of 25-30 fps (typical real-time scenario). Digital video processing has to
process each frame in order to detect a feature on the input. In stereo vision,
existing algorithms use frames from two digital cameras and process them pixel
by pixel until it finds a pattern match in a section of both stereo frames. To
process stereo vision information, an image matching process is essential, but it
needs very high computational cost. Moreover, as more information is
processed, the more time spent by the matching algorithm, the more inefficient
it is. Spike-based processing is a relatively new approach that implements
processing by manipulating spikes one by one at the time they are transmitted,
like a human brain. The mammal nervous system is able to solve much more
complex problems, such as visual recognition by manipulating neuron’s spikes.
The spike-based philosophy for visual information processing based on the
neuro-inspired Address-Event- Representation (AER) is achieving nowadays
very high performances. The aim of this work is to study the viability of a
matching mechanism in a stereo-vision system, using AER codification. This
kind of mechanism has not been done before to an AER system. To do that,
epipolar geometry basis applied to AER system are studied, and several tests
are run, using recorded data and a computer. The results and an average error
are shown (error less than 2 pixels per point); and the viability is proved
On the AER Convolution Processors for FPGA
Image convolution operations in digital computer
systems are usually very expensive operations in terms of
resource consumption (processor resources and processing time)
for an efficient Real-Time application. In these scenarios the
visual information is divided into frames and each one has to be
completely processed before the next frame arrives in order to
warranty the real-time. A spike-based philosophy for computing
convolutions based on the neuro-inspired Address-Event-
Representation (AER) is achieving high performances. In this
paper we present two FPGA implementations of AER-based
convolution processors for relatively small Xilinx FPGAs
(Spartan-II 200 and Spartan-3 400), which process 64x64 images
with 11x11 convolution kernels. The maximum equivalent
operation rate that can be reached is 163.51 MOPS for 11x11
kernels, in a Xilinx Spartan 3 400 FPGA with a 50MHz clock.
Formulations, hardware architecture, operation examples and
performance comparison with frame-based convolution
processors are presented and discussed.Ministerio de Ciencia e Innovación TEC2006-11730-C03-02Ministerio de Ciencia e Innovación TEC2009-10639-C04-02Junta de Andalucía P06-TIC-0141
- …