Magnetless circulators based on linear time-varying circuits

In a crowded electromagnetic spectrum with an ever‐increasing demand for higher data rates to enable multimedia‐rich applications and services, an efficient use of the available wireless resources becomes crucial. For this reason, full‐duplex communication, which doubles the transmission rate over a certain bandwidth compared to currently deployed half-duplex radios by operating the uplink and the downlink simultaneously on the same frequency, has been brought back into the spotlight after decades of being presumed impractical. This long‐held assumption has been particularly due to the lack of high performance low-cost and small-size circulators that could mitigate the strong self-interference at the RF frontend interface of full-duplex transceivers while, at the same time, permitting low-loss bi-directional communication using a single antenna. Traditionally, such non-reciprocal components were almost exclusively based on magnetic biasing of rare-earth ferrite materials, which results in bulky and expensive devices that are not suitable for the vast majority of commercial systems. Despite significant research efforts over the past few decades, none of the previous works managed to eliminate the magnet while satisfying all the challenging requirements dictated by the standards of real systems. In this dissertation, we introduce several newly invented magnetless circulators based on linear time-varying circuits that can overcome for the first time the limitations of all previous approaches. We analyze the presented circuits rigorously and validate them through simulations and measurements, showing unprecedented performance in all relevant metrics, thus holding the promise to enable full-duplex radios in the near futur

Design and implementation of a 20 GHz ultra-wide bandwidth channel emulator for differential high speed serial data links

High speed serial link is now the dominant signal propagation design in various communication, computing and embedded applications. Emulation of such channels is important in signal integrity design and product testing, where full channel simulation is restricted due to the need for protection of intellectual property and frequent channel reconfiguration. This thesis introduces robust lossy material and FIR filter design methods that can be used for channel emulation to provide a solution under these restrictions. Based on the channel characterizations normally obtained in the frequency domain by vector network analysis, different emulation strategies and optimization techniques are utilized to emulate different types of channels. Lossy material overlaid on a microstrip trace can emulate a channel with a smooth loss curve. Likewise, lossy material with an RF FIR filter chip can emulate channel with nonlinear nulls and ripples. The emulation performance is evaluated in the time domain by use of an eye diagram and parameter comparison. During the synthesis of the emulating channel, the physical origins of the channel\u27s time and frequency domain characteristics are analyzed. Furthermore, the hardware realization of the emulation structure is demonstrated with positive examples --Abstract, page iv

Wideband Watt-Level Spatial Power-Combined Power Amplifier in SiGe BiCMOS Technology for Efficient mm-Wave Array Transmitters

The continued demand for high-speed wireless communications is driving the development of integrated high-power transmitters at millimeter wave (mm-Wave) frequencies. Si-based technologies allow achieving a high level of integration but usually provide insufficient generated RF power to compensate for the increased propagation and material losses at mm-Wave bands due to the relatively low breakdown voltage of their devices. This problem can be reduced significantly if one could combine the power of multiple active devices on each antenna element. However, conventional on-chip power combining networks have inherently high insertion losses reducing transmitter efficiency and limiting its maximum achievable output power.This work presents a non-conventional design approach for mm-Wave Si-based Watt-level power amplifiers that is based on novel power-combining architecture, where an array of parallel custom PA-cells suited on the same chip is interfaced to a single substrate integrated waveguide (to be a part of an antenna element). This allows one to directly excite TEm0 waveguide modes with high power through spatial power combining functionality, obviating the need for intermediate and potentially lossy on-chip power combiners. The proposed solution offers wide impedance bandwidth (50%) and low insertion losses (0.4 dB), which are virtually independent from the number of interfaced PA-cells. The work evaluates the scalability bounds of the architecture as well as discusses the critical effects of coupled non-identical PA-cells, which are efficiently reduced by employing on-chip isolation load resistors.The proposed architecture has been demonstrated through an example of the combined PA with four differential cascode PA-cells suited on the same chip, which is flip-chip interconnected to the combiner placed on a laminate. This design is implemented in a 0.25 um SiGe BiCMOS technology. The PA-cell has a wideband performance (38.6%) with both high peak efficiency (30%) and high saturated output power (24.9 dBm), which is the highest reported output power level obtained without the use of circuit-level power combining in Si-based technologies at Ka-band. In order to achieve the optimal system-level performance of the combined PA, an EM-circuit-thermal optimization flow has been proposed, which accounts for various multiphysics effects occurring in the joint structure. The final PA achieves the peak PAE of 26.7% in combination with 30.8 dBm maximum saturated output power, which is the highest achievable output power in practical applications, where the 50-Ohms load is placed on a laminate. The high efficiency (>20%) and output power (>29.8 dBm) over a wide frequency range (30%) exceed the state-of-the-art in Si-based PAs

SiGe Millimeter-Wave (W-Band) Down-Converter for Phased Focal Plane Array

A millimeter-wave (W-Band) down-converter for Phased Focal Plane Arrays (PFPAs) has been designed and fabricated using the IBM Silicon-Germanium (SiGe) BiCMOS 8HP process technology. The radio frequency (RF) input range of the down-converter chip is from 70 95GHz. The intermediate frequency (IF) range is from 5 30GHz. The local oscillator (LO) frequency is fixed at 65GHz. The down-converter chip has been designed to achieve a conversion gain greater than 20dB, a noise figure (NF) below 10dB and input return loss greater than 10dB. The chip also has novel LO circuitry facilitating LO feed-through among down-converters chips in parallel. This wide bandwidth down-converter will be part of millimeter-wave PFPA receiver designed and fabricated in collaboration with the University of Massachusetts-Amherst Department of Astronomy. This PFPA receiver will be installed on Green Bank Telescope (GMT) / Large millimeter wave telescope (LMT) in Q2 of 2014. This project is collaboration between the University of Massachusetts-Amherst (UMass), Brigham Young University (BYU) and National Radio Astronomy Observatory (NRAO). To the best of the author’s knowledge, this is first wide bandwidth down-converter at W-band to achieve this high gain and low noise figure among Si/SiGe based systems

The miniaturization and bandwidth enhancement of printed circuit balun designs for wireless applications

Master'sMASTER OF ENGINEERIN

Push-Pull Based High Efficiency and High Power Broadband Power Amplifiers for Wireless Base Stations

The monthly data throughput by 2021 is forecasted to be ten times that of December 2015. As a result of the on going dramatic increase in demand, service providers are assigned new frequency bands to accommodate more channels to carry more data. However, the usable part of the spectrum is a limited resource so modern communication signals were designed to be more spectrally efficient to send more bits over the same channel bandwidth. However, these spectrally efficient signals have high PAPR. The immediate reaction to these changes was to add additional RF front-end branches to accommodate the new frequency bands. Initially, the PAs used at the time were not optimized for back-off efficiency and where operating at low efficiency which caused significant increase in heat generation for the same average power produced which in turn increased cooling costs and reduced the life time of the PA. After the introduction of back-off efficiency enhancement techniques the PAs became more efficient however they were limited in bandwidth which is typically 10-15%. This work focuses on reducing the redundancy of power amplifiers in communication base stations while maintaining high back-off efficiency. After exploring the literature to understand the limitations of current implementations, it was found that the push-pull topology is often used at low frequency in broadband high power PAs. In the absence of a complimentary transistor pairs the push-pull implantation requires the use of balanced to unbalanced (balun) transformers. Various balun implantations were hence investigated to identify the most suitable option for broadband planar implementation. As a result, a methodology was proposed to co-design the balun and the matching network in order to have better control over the harmonic impedance. An 85 W push-pull PA was then designed based on the proposed methodology with a multi-octave bandwidth as a demonstration of the broadband potential of push-pull PAs at RF frequencies. Next, the two most popular techniques for back-off efficiency enhancement, i.e., ET and load modulation, were studied and the principle of load modulation was found to be more suitable for broadband signal transmission. The Doherty architecture is the most common implementation of load modulation and it comes in two basic variations, the PCL and SCL DPAs. The original architecture concepts are not only band limited but also ill-suited for high frequency designs where the transistors' parasitics introduce significant effect. However, later literature expanded on the original concept of the PCL variation which provided the needed flexibility for wider bandwidth implementations at a higher frequency. Using the broadband implementation and the co-design methodology two push-pull amplifiers were used in a PCL DPA topology and demonstrated that the push-pull utilization doesn't have a significant impact on the bandwidth of the output combiner as an octave bandwidth was achieved with the use of digital Doherty. Lastly, the thesis proposes a new approach for designing high power DPAs with extended bandwidth. It starts with a generic SCL DPA architecture to derive the equations that relate its underlying combiner's ABCD parameters to the transistor's optimum impedance and load impedance. These equations featured the possibility of significantly increasing the load impedance in SCL DPA compared to the one of the popular PCL DPA architecture. This is particularly beneficial when targeting very high power DPAs for macro-cell base stations and broadcast applications where very low load impedance can seriously complicate the design and limit the achievable bandwidth. To further maximize the load impedance increase, the proposed SCL DPA uses a push-pull topology for the main and peaking amplifier stages. A low-loss planar balanced to unbalanced transformer (balun) combiner network is then utilized to realize the SCL DPA combining. The proposed approach was finally applied to design a proof-of-concept 350 W SCL DPA which operates over the band spanning from 720 to 980 MHz. The prototype demonstrated a peak output power of about 55 dBm over a 30% FBW with a 6 dB back-off efficiency, measured using pulsed signal, between 46.6% and 54.6%. Furthermore, the modulated signal based measurement results confirmed the linearizability of the SCL DPA prototype while maintaining a back-off efficiency over 50% for a 7.1 dB peak to average power ratio signal

A 40-GHz Load Modulated Balanced Power Amplifier using Unequal Power Splitter and Phase Compensation Network in 45-nm SOI CMOS

© 2023 IEEE - All rights reserved. This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1109/TCSI.2023.3282731 ​​​​​​​In this work, a ten-way power-combined poweramplifier is designed using a load modulated balanced amplifier(LMBA)-based architecture. To provide the required magnitudeand phase controls between the main and control-signal paths ofthe LMBA, an unequal power splitter and a phase compensationnetwork are proposed. As proof of concept, the designed poweramplifier is implemented in a 45-nm SOI CMOS process. At 40GHz, it delivers a 25.1 dBm Psat with a peak power-addedefficiency (PAE) of 27.9%. At 6-dB power back-off level, itachieves 1.39 times drain efficiency enhancement over an idealClass-B power amplifier. Using a 200-MHz single-carrier 64-QAMsignal, the designed amplifier delivers an average output power of16.5 dBm with a PAE of 13.1% at an EVMrms of -23.9 dB andACPR of -25.3 dBc. The die size, including all testing pads, is only1.92 mm2. To the best of the authors’ knowledge, compared withthe other recently published silicon-based LMBAs, this designachieves the highest Psat.Peer reviewe