Formal hardware verification of digital circuits

The use of formal methods to verify the correctness of digital circuits is less constrained by the growing complexity of digital circuits than conventional methods based on exhaustive simulation. This paper briefly outlines three main approaches to formal hardware verification: symbolic simulation, state machine analysis, and theorem-proving

Temporal constraint reasoning in microprocessor systems diagnosis.

by Yuen Siu Ming.Thesis (M.Phil.)--Chinese University of Hong Kong, 1995.Includes bibliographical references (leaves 104-110).Chapter 1 --- Introduction --- p.1Chapter 2 --- Background --- p.4Chapter 2.1 --- Approaches in Formal Hardware Verification --- p.4Chapter 2.1.1 --- Theorem Proving --- p.5Chapter 2.1.2 --- Symbolic Simulation --- p.5Chapter 2.1.3 --- Model Checking --- p.6Chapter 2.2 --- Temporal Theories --- p.7Chapter 2.3 --- Related Works --- p.8Chapter 2.3.1 --- Consistency and Satisfiability of Timing Specifications --- p.8Chapter 2.3.2 --- Symbolic Constraint Satisfaction --- p.9Chapter 3 --- Problem Domain --- p.11Chapter 3.1 --- Basics of MC68000 Read Cycle --- p.11Chapter 4 --- Knowledge-based System Structure --- p.13Chapter 4.1 --- Diagnostic Reasoning Mechanisms --- p.14Chapter 4.2 --- Occurring Event Sequence --- p.16Chapter 4.3 --- Equivalent Goals --- p.17Chapter 4.4 --- CPU Databus Setup Time --- p.17Chapter 4.5 --- Assertion of CPU AS Signal --- p.19Chapter 5 --- Time Range Approach --- p.21Chapter 5.1 --- Time Range Represent ation --- p.21Chapter 5.2 --- Time Ranges Reasoning Techniques --- p.22Chapter 5.2.1 --- Constraint Satisfaction of Time Ranges --- p.22Chapter 5.2.2 --- Constraint Propagation of Time Ranges --- p.25Chapter 5.3 --- Worst-Case Timing Analysis --- p.28Chapter 5.4 --- System Implementation --- p.29Chapter 5.4.1 --- CPU Databus Setup Time --- p.30Chapter 5.4.2 --- Assertion of CPU AS Signal --- p.36Chapter 5.5 --- Implementation Results --- p.40Chapter 5.5.1 --- CPU Databus Setup Time --- p.40Chapter 5.5.2 --- Assertion of CPU AS Signal --- p.40Chapter 5.6 --- Conclusion --- p.41Chapter 6 --- Fuzzy Time Point Approach --- p.43Chapter 6.1 --- Fuzzy Time Point Models --- p.44Chapter 6.1.1 --- Concept of Fuzzy Numbers --- p.44Chapter 6.1.2 --- Definition of Fuzzy Time Points --- p.45Chapter 6.1.3 --- Semi-bounded Fuzzy Time Points --- p.47Chapter 6.2 --- Fuzzy Time Point Reasoning Techniques --- p.48Chapter 6.2.1 --- Constraint Propagation of Fuzzy Time Points --- p.50Chapter 6.2.2 --- Constraint Satisfaction of Fuzzy Time Points --- p.52Chapter 6.3 --- System Implementation --- p.55Chapter 6.3.1 --- Representation of Fuzzy Time Point --- p.55Chapter 6.3.2 --- Fuzzy Time Point Satisfaction --- p.56Chapter 6.3.3 --- Fuzzy Time Point Propagation --- p.58Chapter 6.4 --- Implementation Results --- p.64Chapter 6.4.1 --- CPU Databus Setup Time --- p.64Chapter 6.4.2 --- Assertion of CPU AS Signal --- p.65Chapter 6.5 --- Fuzzy Time Point Model Parameters --- p.66Chapter 6.5.1 --- Variation of Semi-bounded ftps' Membership Function --- p.66Chapter 6.5.2 --- Variation of μftp --- p.67Chapter 6.5.3 --- Variation of K --- p.69Chapter 6.6 --- Conclusion --- p.69Chapter 7 --- Constraint Compatibility Reasoning --- p.72Chapter 7.1 --- Abstract Timing Parameters --- p.73Chapter 7.2 --- MC68000 Read Cycle: Wait States Insertion --- p.75Chapter 7.3 --- Constraint Compatibility of Fuzzy Time Point --- p.75Chapter 7.3.1 --- Crisp Threshold Value --- p.77Chapter 7.3.2 --- Possibility Quantification for the Number of Wait States --- p.78Chapter 7.3.3 --- Threshold Beyond Fuzzy Time Point --- p.80Chapter 7.3.4 --- Fuzzy Time Point Beyond Threshold --- p.80Chapter 7.3.5 --- Threshold Within Fuzzy Time Point --- p.82Chapter 7.4 --- Determine When CPU Clock State is S5 --- p.83Chapter 7.5 --- System Implementation --- p.84Chapter 7.5.1 --- Expert's Heuristic Rule --- p.84Chapter 7.5.2 --- Constraint Compatibility --- p.85Chapter 7.5.3 --- Wait States Insertion --- p.87Chapter 7.6 --- Implementation Results --- p.91Chapter 7.7 --- Conclusion --- p.93Chapter 8 --- Conclusion --- p.95Chapter 8.1 --- Applications in Other Domains --- p.97Chapter 8.2 --- Future Directions and Recommendations --- p.98Chapter A --- Constraint Compatibility Reasoning Output --- p.99Chapter A.1 --- No Wait Cycle Insertion --- p.99Chapter A.2 --- Single Wait Cycle Insertion --- p.100Chapter A.3 --- Two Wait Cycle Insertions --- p.100Chapter B --- MC68020 Read Cycle Problem --- p.101Chapter B.1 --- Basics of MC68020 Read Cycle --- p.101Chapter B.2 --- MC68020 Databus Setup Time --- p.102Chapter B.3 --- Implementation Results --- p.103Bibliography --- p.10

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2