755 research outputs found
Π Π²ΠΎΠΏΡΠΎΡΡ ΡΠΈΠ½ΡΠ΅Π·Π° Π³Π΅Π½Π΅ΡΠ°ΡΠΎΡΠΎΠ² ΠΌΠΎΠ΄ΠΈΡΠΈΡΠΈΡΠΎΠ²Π°Π½Π½ΡΡ ΠΊΠΎΠ΄ΠΎΠ² Ρ ΡΡΠΌΠΌΠΈΡΠΎΠ²Π°Π½ΠΈΠ΅ΠΌ Π²Π·Π²Π΅ΡΠ΅Π½Π½ΡΡ ΠΈΠ½ΡΠΎΡΠΌΠ°ΡΠΈΠΎΠ½Π½ΡΡ ΡΠ°Π·ΡΡΠ΄ΠΎΠ² Ρ ΠΏΠΎΡΠ»Π΅Π΄ΠΎΠ²Π°ΡΠ΅Π»ΡΠ½ΠΎΡΡΡΡ Π²Π΅ΡΠΎΠ²ΡΡ ΠΊΠΎΡΡΡΠΈΡΠΈΠ΅Π½ΡΠΎΠ², ΠΎΠ±ΡΠ°Π·ΡΡΡΠ΅ΠΉ Π½Π°ΡΡΡΠ°Π»ΡΠ½ΡΠΉ ΡΡΠ΄ ΡΠΈΡΠ΅Π»
ΠΠ·Π»Π°Π³Π°ΡΡΡΡ ΡΠ΅Π·ΡΠ»ΡΡΠ°ΡΡ, ΠΏΠΎΠ»ΡΡΠ΅Π½Π½ΡΠ΅ Π°Π²ΡΠΎΡΠΎΠΌ Π² ΠΎΠ±Π»Π°ΡΡΠΈ ΡΠΈΠ½ΡΠ΅Π·Π° Π³Π΅Π½Π΅ΡΠ°ΡΠΎΡΠΎΠ² ΠΊΠΎΠ½ΡΡΠΎΠ»ΡΠ½ΡΡ
Π²Π΅ΠΊΡΠΎΡΠΎΠ² ΠΌΠΎΠ΄ΠΈΡΠΈΡΠΈΡΠΎΠ²Π°Π½Π½ΡΡ
ΠΊΠΎΠ΄ΠΎΠ² ΠΠ΅ΡΠ³Π΅ΡΠ°. ΠΠ°Π½Π½ΡΠ΅ ΠΊΠΎΠ΄Ρ ΠΏΡΠΈΠ½Π°Π΄Π»Π΅ΠΆΠ°Ρ ΠΊ ΠΊΠ»Π°ΡΡΡ ΠΌΠΎΠ΄ΠΈΡΠΈΡΠΈΡΠΎΠ²Π°Π½Π½ΡΡ
ΠΌΠΎΠ΄ΡΠ»ΡΠ½ΠΎ Π²Π·Π²Π΅ΡΠ΅Π½Π½ΡΡ
ΠΊΠΎΠ΄ΠΎΠ² Ρ ΡΡΠΌΠΌΠΈΡΠΎΠ²Π°Π½ΠΈΠ΅ΠΌ. ΠΡΠΈΠ²ΠΎΠ΄ΡΡΡΡ ΠΎΠ±ΡΠΈΠ΅ ΡΡΡΡΠΊΡΡΡΡ Π³Π΅Π½Π΅ΡΠ°ΡΠΎΡΠΎΠ² ΡΠ°ΠΊΠΈΡ
ΠΊΠΎΠ΄ΠΎΠ², Π° ΡΠ°ΠΊΠΆΠ΅ Π°Π»Π³ΠΎΡΠΈΡΠΌ ΠΏΠΎΡΡΡΠΎΠ΅Π½ΠΈΡ Π³Π΅Π½Π΅ΡΠ°ΡΠΎΡΠ°, ΠΏΠΎΠ·Π²ΠΎΠ»ΡΡΡΠΈΠΉ ΠΎΠΏΡΠΈΠΌΠΈΠ·ΠΈΡΠΎΠ²Π°ΡΡ Π΅Π³ΠΎ ΡΡΡΡΠΊΡΡΡΡ, ΡΠΎΠΊΡΠ°ΡΠΈΠ² ΠΊΠΎΠ»ΠΈΡΠ΅ΡΡΠ²ΠΎ ΠΈΡΠΏΠΎΠ»ΡΠ·ΡΠ΅ΠΌΡΡ
ΡΡΠ½ΠΊΡΠΈΠΎΠ½Π°Π»ΡΠ½ΡΡ
ΡΠ»Π΅ΠΌΠ΅Π½ΡΠΎΠ². ΠΡΠ²ΠΎΠ΄ΠΈΡΡΡ ΡΠΎΡΠΌΡΠ»Π° ΠΏΠΎΠ΄ΡΡΠ΅ΡΠ° ΠΎΠ±ΡΠ΅Π³ΠΎ ΠΊΠΎΠ»ΠΈΡΠ΅ΡΡΠ²Π° Π΄Π²ΡΡ
Π²Ρ
ΠΎΠ΄ΠΎΠ²ΡΡ
Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΈΡ
ΡΠ»Π΅ΠΌΠ΅Π½ΡΠΎΠ², Π½Π΅ΠΎΠ±Ρ
ΠΎΠ΄ΠΈΠΌΡΡ
Π΄Π»Ρ ΡΠ΅Ρ
Π½ΠΈΡΠ΅ΡΠΊΠΎΠΉ ΡΠ΅Π°Π»ΠΈΠ·Π°ΡΠΈΠΈ Π³Π΅Π½Π΅ΡΠ°ΡΠΎΡΠ°. ΠΡΠ΅Π΄Π»ΠΎΠΆΠ΅Π½Π½ΡΠΉ Π°Π»Π³ΠΎΡΠΈΡΠΌ ΡΠΈΠ½ΡΠ΅Π·Π° Π³Π΅Π½Π΅ΡΠ°ΡΠΎΡΠΎΠ² ΡΠ²Π»ΡΠ΅ΡΡΡ ΡΠ½ΠΈΠ²Π΅ΡΡΠ°Π»ΡΠ½ΡΠΌ ΠΈ ΠΌΠΎΠΆΠ΅Ρ Π±ΡΡΡ ΠΈΡΠΏΠΎΠ»ΡΠ·ΠΎΠ²Π°Π½ Π΄Π»Ρ ΠΏΠΎΡΡΡΠΎΠ΅Π½ΠΈΡ Π³Π΅Π½Π΅ΡΠ°ΡΠΎΡΠΎΠ² Π»ΡΠ±ΡΡ
ΠΌΠΎΠ΄ΠΈΡΠΈΡΠΈΡΠΎΠ²Π°Π½Π½ΡΡ
ΠΌΠΎΠ΄ΡΠ»ΡΠ½ΠΎ Π²Π·Π²Π΅ΡΠ΅Π½Π½ΡΡ
ΠΊΠΎΠ΄ΠΎΠ² Ρ ΡΡΠΌΠΌΠΈΡΠΎΠ²Π°Π½ΠΈΠ΅ΠΌ
Optimization of FPGA Based Neural Network Processor
Neural information processing is an emerging new field, providing an alternative
form of computation for demanding tasks such as pattern recognition problems
which are usually reserved for human attention. Neural network computation i s
sought after where classification of input data is difficult to be worked out using
equations or sets of rules.
Technological advances in integrated circuits such as Field Programmable Gate
Array (FPGA) systems have made it easier to develop and implement hardware
devices based on these neural network architectures. The motivation in hardware
implementation of neural networks is its fast processing speed and suitability in
parallel and pipelined processing.
The project revolves around the design of an optimized neural network processor.
The processor design is based on the feedforward network architecture type with
BackPropagation trained weights for the Exclusive-OR non-linear problem.
Among the highlights of the project is the improvement in neural network
architecture through reconfigurable and recursive computation of a single hidden
layer for multiple layer applications. Improvements in processor organization were
also made which enables the design to parallel process with similar processors.
Other improvements include design considerations to reduce the amount of logic
required for implementation without much sacrifice of processing speed
ΠΠ΅ΡΠΎΠ΄ ΠΎΠΏΡΠ΅Π΄Π΅Π»Π΅Π½ΠΈΡ ΡΡΠ½ΠΊΡΠΈΠΎΠ½Π°Π»ΡΠ½ΠΎΠΉ Π·Π°Π²ΠΈΡΠΈΠΌΠΎΡΡΠΈ ΡΠ°Π±ΠΎΡΠΈΡ Π²ΡΡ ΠΎΠ΄ΠΎΠ² Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΈΡ ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΎΠ½Π½ΡΡ ΡΡ Π΅ΠΌ ΠΎΡ ΠΏΡΠΎΡΠ²Π»Π΅Π½ΠΈΡ ΠΌΠΎΠ½ΠΎΡΠΎΠ½Π½ΡΡ ΠΎΡΠΈΠ±ΠΎΠΊ
Structural dependences of the working outputs of logical combinational circuits were studied with the aim of subsequent identification of the type of possible errors. The types of manifested errors and the classification of the working outputs of logical combinational circuits are given. It is shown that the presence of an internal structural connection of discrete devices leads to an increase in the multiplicity of possible errors. The condition for determining the functional dependence of outputs on the manifestation of errors of the studied multiplicity is given. It is noted that out of the many types of errors, unidirectional errors can appear at the outputs of the circuits. A well-known method for determining unidirectionally dependent operating outputs of discrete device circuits is presented, which has a drawback. It is only necessary to pairwise compare each output with the rest of the whole set. For the convenience of the process of searching for such outputs, the author of the article proposed a new method for identifying unidirectionally dependent working outputs. This method differs from known methods in that it is applicable for any number of outputs, which requires much less time to search for the above outputs. It is shown that logical combinational circuits can have functional features, in which only unidirectional errors can appear at the working outputs. Therefore, a new method for identifying any number of unidirectionally independent operating outputs of combinational circuits has been proposed. It is shown that the methods proposed in the article for finding unidirectionally dependent and unidirectionally independent outputs of logical combinational circuits require simple mathematical calculations. In the Multisim, internal faults of the diagnosable circuits are simulated and all possible errors at the working outputs are fixed. According to the results of the experiments, the validity of the theoretical results obtained was also confirmed.Π ΡΠ°Π±ΠΎΡΠ΅ ΠΈΡΡΠ»Π΅Π΄ΠΎΠ²Π°Π½Ρ ΡΡΡΡΠΊΡΡΡΠ½ΡΠ΅ Π·Π°Π²ΠΈΡΠΈΠΌΠΎΡΡΠΈ ΡΠ°Π±ΠΎΡΠΈΡ
Π²ΡΡ
ΠΎΠ΄ΠΎΠ² Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΈΡ
ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΎΠ½Π½ΡΡ
ΡΡ
Π΅ΠΌ Ρ ΡΠ΅Π»ΡΡ ΠΏΠΎΡΠ»Π΅Π΄ΡΡΡΠ΅ΠΉ ΠΈΠ΄Π΅Π½ΡΠΈΡΠΈΠΊΠ°ΡΠΈΠΈ Π²ΠΈΠ΄Π° Π²ΠΎΠ·ΠΌΠΎΠΆΠ½ΡΡ
ΠΎΡΠΈΠ±ΠΎΠΊ. ΠΡΠΈΠ²Π΅Π΄Π΅Π½Ρ Π²ΠΈΠ΄Ρ Π²ΠΎΠ·Π½ΠΈΠΊΠ°ΡΡΠΈΡ
ΠΎΡΠΈΠ±ΠΎΠΊ ΠΈ ΠΊΠ»Π°ΡΡΠΈΡΠΈΠΊΠ°ΡΠΈΡ ΡΠ°Π±ΠΎΡΠΈΡ
Π²ΡΡ
ΠΎΠ΄ΠΎΠ² Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΈΡ
ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΎΠ½Π½ΡΡ
ΡΡ
Π΅ΠΌ. ΠΠΎΠΊΠ°Π·Π°Π½ΠΎ, ΡΡΠΎ Π½Π°Π»ΠΈΡΠΈΠ΅ Π²Π½ΡΡΡΠ΅Π½Π½Π΅ΠΉ ΡΡΡΡΠΊΡΡΡΠ½ΠΎΠΉ ΡΠ²ΡΠ·ΠΈ Π΄ΠΈΡΠΊΡΠ΅ΡΠ½ΡΡ
ΡΡΡΡΠΎΠΉΡΡΠ² ΠΏΡΠΈΠ²ΠΎΠ΄ΠΈΡ ΠΊ ΡΠ²Π΅Π»ΠΈΡΠ΅Π½ΠΈΡ ΠΊΡΠ°ΡΠ½ΠΎΡΡΠΈ Π²ΠΎΠ·ΠΌΠΎΠΆΠ½ΡΡ
ΠΎΡΠΈΠ±ΠΎΠΊ. ΠΡΠΈΠ²ΠΎΠ΄ΠΈΡΡΡ ΡΡΠ»ΠΎΠ²ΠΈΠ΅ ΠΎΠΏΡΠ΅Π΄Π΅Π»Π΅Π½ΠΈΡ ΡΡΠ½ΠΊΡΠΈΠΎΠ½Π°Π»ΡΠ½ΠΎΠΉ Π·Π°Π²ΠΈΡΠΈΠΌΠΎΡΡΠΈ Π²ΡΡ
ΠΎΠ΄ΠΎΠ² ΠΎΡ ΠΏΡΠΎΡΠ²Π»Π΅Π½ΠΈΡ ΠΎΡΠΈΠ±ΠΎΠΊ ΠΈΡΡΠ»Π΅Π΄ΡΠ΅ΠΌΠΎΠΉ ΠΊΡΠ°ΡΠ½ΠΎΡΡΠΈ. ΠΡΠΌΠ΅ΡΠ΅Π½ΠΎ, ΡΡΠΎ ΠΈΠ· ΠΌΠ½ΠΎΠΆΠ΅ΡΡΠ²Π° Π²ΠΈΠ΄ΠΎΠ² ΠΎΡΠΈΠ±ΠΎΠΊ, Π½Π° Π²ΡΡ
ΠΎΠ΄Π°Ρ
ΡΡ
Π΅ΠΌ ΠΌΠΎΠ³ΡΡ ΠΏΡΠΎΡΠ²Π»ΡΡΡΡΡ ΠΎΠ΄Π½ΠΎΠ½Π°ΠΏΡΠ°Π²Π»Π΅Π½Π½ΡΠ΅ (ΠΌΠΎΠ½ΠΎΡΠΎΠ½Π½ΡΠ΅) ΠΎΡΠΈΠ±ΠΊΠΈ. ΠΡΠΈΠ²Π΅Π΄Π΅Π½ ΠΈΠ·Π²Π΅ΡΡΠ½ΡΠΉ ΠΌΠ΅ΡΠΎΠ΄ ΠΎΠΏΡΠ΅Π΄Π΅Π»Π΅Π½ΠΈΡ ΠΌΠΎΠ½ΠΎΡΠΎΠ½Π½ΠΎ Π·Π°Π²ΠΈΡΠΈΠΌΡΡ
ΡΠ°Π±ΠΎΡΠΈΡ
Π²ΡΡ
ΠΎΠ΄ΠΎΠ² Π΄ΠΈΡΠΊΡΠ΅ΡΠ½ΡΡ
ΡΡΡΡΠΎΠΉΡΡΠ² ΠΈ ΡΠΊΠ°Π·Π°Π½ Π΅Π³ΠΎ Π½Π΅Π΄ΠΎΡΡΠ°ΡΠΎΠΊ, Π·Π°ΠΊΠ»ΡΡΠ°ΡΡΠΈΠΉΡΡ Π² Π½Π΅ΠΎΠ±Ρ
ΠΎΠ΄ΠΈΠΌΠΎΡΡΠΈ ΡΠΎΠ»ΡΠΊΠΎ ΠΏΠΎΠΏΠ°ΡΠ½ΠΎΠ³ΠΎ ΡΡΠ°Π²Π½Π΅Π½ΠΈΡ ΠΊΠ°ΠΆΠ΄ΠΎΠ³ΠΎ Π²ΡΡ
ΠΎΠ΄Π° Ρ ΠΎΡΡΠ°Π»ΡΠ½ΡΠΌΠΈ ΠΈΠ· ΡΠ΅Π»ΠΎΠ³ΠΎ ΠΌΠ½ΠΎΠΆΠ΅ΡΡΠ²Π°. ΠΠ»Ρ ΡΠ΄ΠΎΠ±ΡΡΠ²Π° ΠΏΡΠΎΡΠ΅ΡΡΠ° ΠΏΠΎΠΈΡΠΊΠ° ΠΏΠΎΠ΄ΠΎΠ±Π½ΡΡ
Π²ΡΡ
ΠΎΠ΄ΠΎΠ² Π°Π²ΡΠΎΡΠΎΠΌ ΡΡΠ°ΡΡΠΈ ΠΏΡΠ΅Π΄Π»ΠΎΠΆΠ΅Π½ Π½ΠΎΠ²ΡΠΉ ΠΌΠ΅ΡΠΎΠ΄ ΠΈΠ΄Π΅Π½ΡΠΈΡΠΈΠΊΠ°ΡΠΈΠΈ ΠΌΠΎΠ½ΠΎΡΠΎΠ½Π½ΠΎ Π·Π°Π²ΠΈΡΠΈΠΌΡΡ
ΡΠ°Π±ΠΎΡΠΈΡ
Π²ΡΡ
ΠΎΠ΄ΠΎΠ², ΠΎΡΠ»ΠΈΡΠ°ΡΡΠΈΠΉΡΡ ΠΎΡ ΠΈΠ·Π²Π΅ΡΡΠ½ΡΡ
ΠΌΠ΅ΡΠΎΠ΄ΠΎΠ² ΡΠ΅ΠΌ, ΡΡΠΎ Π΄Π°Π½Π½ΡΠΉ ΠΌΠ΅ΡΠΎΠ΄ ΠΏΡΠΈΠΌΠ΅Π½ΠΈΠΌ Π΄Π»Ρ Π»ΡΠ±ΠΎΠ³ΠΎ ΡΠΈΡΠ»Π° Π²ΡΡ
ΠΎΠ΄ΠΎΠ², ΡΡΠΎ ΡΡΠ΅Π±ΡΠ΅Ρ Π·Π½Π°ΡΠΈΡΠ΅Π»ΡΠ½ΠΎ ΠΌΠ΅Π½ΡΡΠ΅Π³ΠΎ Π²ΡΠ΅ΠΌΠ΅Π½ΠΈ Π΄Π»Ρ ΠΏΠΎΠΈΡΠΊΠ° Π²ΡΡΠ΅ΠΏΡΠΈΠ²Π΅Π΄Π΅Π½Π½ΡΡ
Π²ΡΡ
ΠΎΠ΄ΠΎΠ². ΠΠΎΠΊΠ°Π·Π°Π½ΠΎ, ΡΡΠΎ Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΈΠ΅ ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΎΠ½Π½ΡΠ΅ ΡΡ
Π΅ΠΌΡ ΠΌΠΎΠ³ΡΡ ΠΎΠ±Π»Π°Π΄Π°ΡΡ ΡΡΠ½ΠΊΡΠΈΠΎΠ½Π°Π»ΡΠ½ΡΠΌΠΈ ΠΎΡΠΎΠ±Π΅Π½Π½ΠΎΡΡΡΠΌΠΈ, ΠΏΡΠΈ ΠΊΠΎΡΠΎΡΡΡ
Π½Π° ΡΠ°Π±ΠΎΡΠΈΡ
Π²ΡΡ
ΠΎΠ΄Π°Ρ
ΠΌΠΎΠ³ΡΡ ΠΏΡΠΎΡΠ²Π»ΡΡΡΡΡ ΡΠΎΠ»ΡΠΊΠΎ ΠΌΠΎΠ½ΠΎΡΠΎΠ½Π½ΡΠ΅ ΠΎΡΠΈΠ±ΠΊΠΈ. Π‘Π»Π΅Π΄ΠΎΠ²Π°ΡΠ΅Π»ΡΠ½ΠΎ, ΠΏΡΠ΅Π΄Π»ΠΎΠΆΠ΅Π½ Π½ΠΎΠ²ΡΠΉ ΠΌΠ΅ΡΠΎΠ΄ ΠΈΠ΄Π΅Π½ΡΠΈΡΠΈΠΊΠ°ΡΠΈΠΈ Π»ΡΠ±ΠΎΠ³ΠΎ ΡΠΈΡΠ»Π° ΠΌΠΎΠ½ΠΎΡΠΎΠ½Π½ΠΎ Π½Π΅Π·Π°Π²ΠΈΡΠΈΠΌΡΡ
ΡΠ°Π±ΠΎΡΠΈΡ
Π²ΡΡ
ΠΎΠ΄ΠΎΠ² ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΎΠ½Π½ΡΡ
ΡΡ
Π΅ΠΌ. ΠΠΎΠΊΠ°Π·Π°Π½ΠΎ, ΡΡΠΎ ΠΏΡΠ΅Π΄Π»Π°Π³Π°Π΅ΠΌΡΠ΅ Π² ΡΡΠ°ΡΡΠ΅ ΠΌΠ΅ΡΠΎΠ΄Ρ ΠΏΠΎΠΈΡΠΊΠ° ΠΌΠΎΠ½ΠΎΡΠΎΠ½Π½ΠΎ Π·Π°Π²ΠΈΡΠΈΠΌΡΡ
ΠΈ ΠΌΠΎΠ½ΠΎΡΠΎΠ½Π½ΠΎ Π½Π΅Π·Π°Π²ΠΈΡΠΈΠΌΡΡ
Π²ΡΡ
ΠΎΠ΄ΠΎΠ² Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΈΡ
ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΎΠ½Π½ΡΡ
ΡΡ
Π΅ΠΌ ΡΡΠ΅Π±ΡΡΡ Π²ΡΠΏΠΎΠ»Π½Π΅Π½ΠΈΡ Π½Π΅ΡΠ»ΠΎΠΆΠ½ΡΡ
ΠΌΠ°ΡΠ΅ΠΌΠ°ΡΠΈΡΠ΅ΡΠΊΠΈΡ
Π²ΡΡΠΈΡΠ»Π΅Π½ΠΈΠΉ. Π ΠΏΡΠΎΠ³ΡΠ°ΠΌΠΌΠ½ΠΎΠΉ ΡΡΠ΅Π΄Π΅ Multisim ΡΠΌΠΎΠ΄Π΅Π»ΠΈΡΠΎΠ²Π°Π½Ρ Π²Π½ΡΡΡΠ΅Π½Π½ΠΈΠ΅ Π½Π΅ΠΈΡΠΏΡΠ°Π²Π½ΠΎΡΡΠΈ Π΄ΠΈΠ°Π³Π½ΠΎΡΡΠΈΡΡΠ΅ΠΌΡΡ
ΡΡ
Π΅ΠΌ ΠΈ Π·Π°ΡΠΈΠΊΡΠΈΡΠΎΠ²Π°Π½Ρ Π²ΡΠ΅ Π²ΠΎΠ·ΠΌΠΎΠΆΠ½ΡΠ΅ ΠΎΡΠΈΠ±ΠΊΠΈ Π½Π° ΡΠ°Π±ΠΎΡΠΈΡ
Π²ΡΡ
ΠΎΠ΄Π°Ρ
. ΠΠΎ ΡΠ΅Π·ΡΠ»ΡΡΠ°ΡΠ°ΠΌ ΡΠΊΡΠΏΠ΅ΡΠΈΠΌΠ΅Π½ΡΠΎΠ² ΡΠ°ΠΊΠΆΠ΅ ΠΏΠΎΠ΄ΡΠ²Π΅ΡΠΆΠ΄Π΅Π½Π° ΡΠΏΡΠ°Π²Π΅Π΄Π»ΠΈΠ²ΠΎΡΡΡ ΠΏΠΎΠ»ΡΡΠ΅Π½Π½ΡΡ
ΡΠ΅ΠΎΡΠ΅ΡΠΈΡΠ΅ΡΠΊΠΈΡ
ΡΠ΅Π·ΡΠ»ΡΡΠ°ΡΠΎΠ²
ΠΠ΅ΡΠΎΠ΄ ΠΎΠΏΡΠ΅Π΄Π΅Π»Π΅Π½ΠΈΡ ΡΡΠ½ΠΊΡΠΈΠΎΠ½Π°Π»ΡΠ½ΠΎΠΉ Π·Π°Π²ΠΈΡΠΈΠΌΠΎΡΡΠΈ ΡΠ°Π±ΠΎΡΠΈΡ Π²ΡΡ ΠΎΠ΄ΠΎΠ² Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΈΡ ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΎΠ½Π½ΡΡ ΡΡ Π΅ΠΌ ΠΎΡ ΠΏΡΠΎΡΠ²Π»Π΅Π½ΠΈΡ ΠΌΠΎΠ½ΠΎΡΠΎΠ½Π½ΡΡ ΠΎΡΠΈΠ±ΠΎΠΊ
Π ΡΠ°Π±ΠΎΡΠ΅ ΠΈΡΡΠ»Π΅Π΄ΠΎΠ²Π°Π½Ρ ΡΡΡΡΠΊΡΡΡΠ½ΡΠ΅ Π·Π°Π²ΠΈΡΠΈΠΌΠΎΡΡΠΈ ΡΠ°Π±ΠΎΡΠΈΡ
Π²ΡΡ
ΠΎΠ΄ΠΎΠ² Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΈΡ
ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΎΠ½Π½ΡΡ
ΡΡ
Π΅ΠΌ Ρ ΡΠ΅Π»ΡΡ ΠΏΠΎΡΠ»Π΅Π΄ΡΡΡΠ΅ΠΉ ΠΈΠ΄Π΅Π½ΡΠΈΡΠΈΠΊΠ°ΡΠΈΠΈ Π²ΠΈΠ΄Π° Π²ΠΎΠ·ΠΌΠΎΠΆΠ½ΡΡ
ΠΎΡΠΈΠ±ΠΎΠΊ. ΠΡΠΈΠ²Π΅Π΄Π΅Π½Ρ Π²ΠΈΠ΄Ρ Π²ΠΎΠ·Π½ΠΈΠΊΠ°ΡΡΠΈΡ
ΠΎΡΠΈΠ±ΠΎΠΊ ΠΈ ΠΊΠ»Π°ΡΡΠΈΡΠΈΠΊΠ°ΡΠΈΡ ΡΠ°Π±ΠΎΡΠΈΡ
Π²ΡΡ
ΠΎΠ΄ΠΎΠ² Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΈΡ
ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΎΠ½Π½ΡΡ
ΡΡ
Π΅ΠΌ. ΠΠΎΠΊΠ°Π·Π°Π½ΠΎ, ΡΡΠΎ Π½Π°Π»ΠΈΡΠΈΠ΅ Π²Π½ΡΡΡΠ΅Π½Π½Π΅ΠΉ ΡΡΡΡΠΊΡΡΡΠ½ΠΎΠΉ ΡΠ²ΡΠ·ΠΈ Π΄ΠΈΡΠΊΡΠ΅ΡΠ½ΡΡ
ΡΡΡΡΠΎΠΉΡΡΠ² ΠΏΡΠΈΠ²ΠΎΠ΄ΠΈΡ ΠΊ ΡΠ²Π΅Π»ΠΈΡΠ΅Π½ΠΈΡ ΠΊΡΠ°ΡΠ½ΠΎΡΡΠΈ Π²ΠΎΠ·ΠΌΠΎΠΆΠ½ΡΡ
ΠΎΡΠΈΠ±ΠΎΠΊ. ΠΡΠΈΠ²ΠΎΠ΄ΠΈΡΡΡ ΡΡΠ»ΠΎΠ²ΠΈΠ΅ ΠΎΠΏΡΠ΅Π΄Π΅Π»Π΅Π½ΠΈΡ ΡΡΠ½ΠΊΡΠΈΠΎΠ½Π°Π»ΡΠ½ΠΎΠΉ Π·Π°Π²ΠΈΡΠΈΠΌΠΎΡΡΠΈ Π²ΡΡ
ΠΎΠ΄ΠΎΠ² ΠΎΡ ΠΏΡΠΎΡΠ²Π»Π΅Π½ΠΈΡ ΠΎΡΠΈΠ±ΠΎΠΊ ΠΈΡΡΠ»Π΅Π΄ΡΠ΅ΠΌΠΎΠΉ ΠΊΡΠ°ΡΠ½ΠΎΡΡΠΈ. ΠΡΠΌΠ΅ΡΠ΅Π½ΠΎ, ΡΡΠΎ ΠΈΠ· ΠΌΠ½ΠΎΠΆΠ΅ΡΡΠ²Π° Π²ΠΈΠ΄ΠΎΠ² ΠΎΡΠΈΠ±ΠΎΠΊ, Π½Π° Π²ΡΡ
ΠΎΠ΄Π°Ρ
ΡΡ
Π΅ΠΌ ΠΌΠΎΠ³ΡΡ ΠΏΡΠΎΡΠ²Π»ΡΡΡΡΡ ΠΎΠ΄Π½ΠΎΠ½Π°ΠΏΡΠ°Π²Π»Π΅Π½Π½ΡΠ΅ (ΠΌΠΎΠ½ΠΎΡΠΎΠ½Π½ΡΠ΅) ΠΎΡΠΈΠ±ΠΊΠΈ. ΠΡΠΈΠ²Π΅Π΄Π΅Π½ ΠΈΠ·Π²Π΅ΡΡΠ½ΡΠΉ ΠΌΠ΅ΡΠΎΠ΄ ΠΎΠΏΡΠ΅Π΄Π΅Π»Π΅Π½ΠΈΡ ΠΌΠΎΠ½ΠΎΡΠΎΠ½Π½ΠΎ Π·Π°Π²ΠΈΡΠΈΠΌΡΡ
ΡΠ°Π±ΠΎΡΠΈΡ
Π²ΡΡ
ΠΎΠ΄ΠΎΠ² Π΄ΠΈΡΠΊΡΠ΅ΡΠ½ΡΡ
ΡΡΡΡΠΎΠΉΡΡΠ² ΠΈ ΡΠΊΠ°Π·Π°Π½ Π΅Π³ΠΎ Π½Π΅Π΄ΠΎΡΡΠ°ΡΠΎΠΊ, Π·Π°ΠΊΠ»ΡΡΠ°ΡΡΠΈΠΉΡΡ Π² Π½Π΅ΠΎΠ±Ρ
ΠΎΠ΄ΠΈΠΌΠΎΡΡΠΈ ΡΠΎΠ»ΡΠΊΠΎ ΠΏΠΎΠΏΠ°ΡΠ½ΠΎΠ³ΠΎ ΡΡΠ°Π²Π½Π΅Π½ΠΈΡ ΠΊΠ°ΠΆΠ΄ΠΎΠ³ΠΎ Π²ΡΡ
ΠΎΠ΄Π° Ρ ΠΎΡΡΠ°Π»ΡΠ½ΡΠΌΠΈ ΠΈΠ· ΡΠ΅Π»ΠΎΠ³ΠΎ ΠΌΠ½ΠΎΠΆΠ΅ΡΡΠ²Π°. ΠΠ»Ρ ΡΠ΄ΠΎΠ±ΡΡΠ²Π° ΠΏΡΠΎΡΠ΅ΡΡΠ° ΠΏΠΎΠΈΡΠΊΠ° ΠΏΠΎΠ΄ΠΎΠ±Π½ΡΡ
Π²ΡΡ
ΠΎΠ΄ΠΎΠ² Π°Π²ΡΠΎΡΠΎΠΌ ΡΡΠ°ΡΡΠΈ ΠΏΡΠ΅Π΄Π»ΠΎΠΆΠ΅Π½ Π½ΠΎΠ²ΡΠΉ ΠΌΠ΅ΡΠΎΠ΄ ΠΈΠ΄Π΅Π½ΡΠΈΡΠΈΠΊΠ°ΡΠΈΠΈ ΠΌΠΎΠ½ΠΎΡΠΎΠ½Π½ΠΎ Π·Π°Π²ΠΈΡΠΈΠΌΡΡ
ΡΠ°Π±ΠΎΡΠΈΡ
Π²ΡΡ
ΠΎΠ΄ΠΎΠ², ΠΎΡΠ»ΠΈΡΠ°ΡΡΠΈΠΉΡΡ ΠΎΡ ΠΈΠ·Π²Π΅ΡΡΠ½ΡΡ
ΠΌΠ΅ΡΠΎΠ΄ΠΎΠ² ΡΠ΅ΠΌ, ΡΡΠΎ Π΄Π°Π½Π½ΡΠΉ ΠΌΠ΅ΡΠΎΠ΄ ΠΏΡΠΈΠΌΠ΅Π½ΠΈΠΌ Π΄Π»Ρ Π»ΡΠ±ΠΎΠ³ΠΎ ΡΠΈΡΠ»Π° Π²ΡΡ
ΠΎΠ΄ΠΎΠ², ΡΡΠΎ ΡΡΠ΅Π±ΡΠ΅Ρ Π·Π½Π°ΡΠΈΡΠ΅Π»ΡΠ½ΠΎ ΠΌΠ΅Π½ΡΡΠ΅Π³ΠΎ Π²ΡΠ΅ΠΌΠ΅Π½ΠΈ Π΄Π»Ρ ΠΏΠΎΠΈΡΠΊΠ° Π²ΡΡΠ΅ΠΏΡΠΈΠ²Π΅Π΄Π΅Π½Π½ΡΡ
Π²ΡΡ
ΠΎΠ΄ΠΎΠ². ΠΠΎΠΊΠ°Π·Π°Π½ΠΎ, ΡΡΠΎ Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΈΠ΅ ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΎΠ½Π½ΡΠ΅ ΡΡ
Π΅ΠΌΡ ΠΌΠΎΠ³ΡΡ ΠΎΠ±Π»Π°Π΄Π°ΡΡ ΡΡΠ½ΠΊΡΠΈΠΎΠ½Π°Π»ΡΠ½ΡΠΌΠΈ ΠΎΡΠΎΠ±Π΅Π½Π½ΠΎΡΡΡΠΌΠΈ, ΠΏΡΠΈ ΠΊΠΎΡΠΎΡΡΡ
Π½Π° ΡΠ°Π±ΠΎΡΠΈΡ
Π²ΡΡ
ΠΎΠ΄Π°Ρ
ΠΌΠΎΠ³ΡΡ ΠΏΡΠΎΡΠ²Π»ΡΡΡΡΡ ΡΠΎΠ»ΡΠΊΠΎ ΠΌΠΎΠ½ΠΎΡΠΎΠ½Π½ΡΠ΅ ΠΎΡΠΈΠ±ΠΊΠΈ. Π‘Π»Π΅Π΄ΠΎΠ²Π°ΡΠ΅Π»ΡΠ½ΠΎ, ΠΏΡΠ΅Π΄Π»ΠΎΠΆΠ΅Π½ Π½ΠΎΠ²ΡΠΉ ΠΌΠ΅ΡΠΎΠ΄ ΠΈΠ΄Π΅Π½ΡΠΈΡΠΈΠΊΠ°ΡΠΈΠΈ Π»ΡΠ±ΠΎΠ³ΠΎ ΡΠΈΡΠ»Π° ΠΌΠΎΠ½ΠΎΡΠΎΠ½Π½ΠΎ Π½Π΅Π·Π°Π²ΠΈΡΠΈΠΌΡΡ
ΡΠ°Π±ΠΎΡΠΈΡ
Π²ΡΡ
ΠΎΠ΄ΠΎΠ² ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΎΠ½Π½ΡΡ
ΡΡ
Π΅ΠΌ. ΠΠΎΠΊΠ°Π·Π°Π½ΠΎ, ΡΡΠΎ ΠΏΡΠ΅Π΄Π»Π°Π³Π°Π΅ΠΌΡΠ΅ Π² ΡΡΠ°ΡΡΠ΅ ΠΌΠ΅ΡΠΎΠ΄Ρ ΠΏΠΎΠΈΡΠΊΠ° ΠΌΠΎΠ½ΠΎΡΠΎΠ½Π½ΠΎ Π·Π°Π²ΠΈΡΠΈΠΌΡΡ
ΠΈ ΠΌΠΎΠ½ΠΎΡΠΎΠ½Π½ΠΎ Π½Π΅Π·Π°Π²ΠΈΡΠΈΠΌΡΡ
Π²ΡΡ
ΠΎΠ΄ΠΎΠ² Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΈΡ
ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΎΠ½Π½ΡΡ
ΡΡ
Π΅ΠΌ ΡΡΠ΅Π±ΡΡΡ Π²ΡΠΏΠΎΠ»Π½Π΅Π½ΠΈΡ Π½Π΅ΡΠ»ΠΎΠΆΠ½ΡΡ
ΠΌΠ°ΡΠ΅ΠΌΠ°ΡΠΈΡΠ΅ΡΠΊΠΈΡ
Π²ΡΡΠΈΡΠ»Π΅Π½ΠΈΠΉ. Π ΠΏΡΠΎΠ³ΡΠ°ΠΌΠΌΠ½ΠΎΠΉ ΡΡΠ΅Π΄Π΅ Multisim ΡΠΌΠΎΠ΄Π΅Π»ΠΈΡΠΎΠ²Π°Π½Ρ Π²Π½ΡΡΡΠ΅Π½Π½ΠΈΠ΅ Π½Π΅ΠΈΡΠΏΡΠ°Π²Π½ΠΎΡΡΠΈ Π΄ΠΈΠ°Π³Π½ΠΎΡΡΠΈΡΡΠ΅ΠΌΡΡ
ΡΡ
Π΅ΠΌ ΠΈ Π·Π°ΡΠΈΠΊΡΠΈΡΠΎΠ²Π°Π½Ρ Π²ΡΠ΅ Π²ΠΎΠ·ΠΌΠΎΠΆΠ½ΡΠ΅ ΠΎΡΠΈΠ±ΠΊΠΈ Π½Π° ΡΠ°Π±ΠΎΡΠΈΡ
Π²ΡΡ
ΠΎΠ΄Π°Ρ
. ΠΠΎ ΡΠ΅Π·ΡΠ»ΡΡΠ°ΡΠ°ΠΌ ΡΠΊΡΠΏΠ΅ΡΠΈΠΌΠ΅Π½ΡΠΎΠ² ΡΠ°ΠΊΠΆΠ΅ ΠΏΠΎΠ΄ΡΠ²Π΅ΡΠΆΠ΄Π΅Π½Π° ΡΠΏΡΠ°Π²Π΅Π΄Π»ΠΈΠ²ΠΎΡΡΡ ΠΏΠΎΠ»ΡΡΠ΅Π½Π½ΡΡ
ΡΠ΅ΠΎΡΠ΅ΡΠΈΡΠ΅ΡΠΊΠΈΡ
ΡΠ΅Π·ΡΠ»ΡΡΠ°ΡΠΎΠ²
Reliability-energy-performance optimisation in combinational circuits in presence of soft errors
PhD ThesisThe reliability metric has a direct relationship to the amount of value produced
by a circuit, similar to the performance metric. With advances in CMOS
technology, digital circuits become increasingly more susceptible to soft errors.
Therefore, it is imperative to be able to assess and improve the level of reliability
of these circuits. A framework for evaluating and improving the reliability of
combinational circuits is proposed, and an interplay between the metrics of
reliability, energy and performance is explored.
Reliability evaluation is divided into two levels of characterisation: stochastic
fault model (SFM) of the component library and a design-specific critical vector
model (CVM). The SFM captures the properties of components with regard to
the interference which causes error. The CVM is derived from a limited number
of simulation runs on the specific design at the design time and producing
the reliability metric. The idea is to move the high-complexity problem of the
stochastic characterisation of components to the generic part of the design
process, and to do it just once for a large number of specific designs. The
method is demonstrated on a range of circuits with various structures.
A three-way trade-off between reliability, energy, and performance has
been discovered; this trade-off facilitates optimisations of circuits and their
operating conditions.
A technique for improving the reliability of a circuit is proposed, based on
adding a slow stage at the primary output. Slow stages have the ability to
absorb narrow glitches from prior stages, thus reducing the error probability.
Such stages, or filters, suppress most of the glitches generated in prior stages
and prevent them from arriving at the primary output of the circuit. Two filter
solutions have been developed and analysed. The results show a dramatic
improvement in reliability at the expense of minor performance and energy
penalties.
To alleviate the problem of the time-consuming analogue simulations involved in the proposed method, a simplification technique is proposed. This
technique exploits the equivalence between the properties of the gates within
a path and the equivalence between paths. On the basis of these equivalences,
it is possible to reduce the number of simulation runs. The effectiveness of
the proposed technique is evaluated by applying it to different circuits with
a representative variety of path topologies. The results show a significant
decrease in the time taken to estimate reliability at the expense of a minor
decrease in the accuracy of estimation. The simplification technique enables
the use of the proposed method in applications with complex circuits.Ministry of Education and Scientific Research in Liby
Π‘ΠΈΠ½ΡΠ΅Π· ΡΠ°ΠΌΠΎΠΏΡΠΎΠ²Π΅ΡΡΠ΅ΠΌΡΡ ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΎΠ½Π½ΡΡ ΡΡΡΡΠΎΠΉΡΡΠ² Π½Π° ΠΎΡΠ½ΠΎΠ²Π΅ ΠΊΠΎΠ΄ΠΎΠ² Ρ ΡΡΡΠ΅ΠΊΡΠΈΠ²Π½ΡΠΌ ΠΎΠ±Π½Π°ΡΡΠΆΠ΅Π½ΠΈΠ΅ΠΌ ΡΠΈΠΌΠΌΠ΅ΡΡΠΈΡΠ½ΡΡ ΠΎΡΠΈΠ±ΠΎΠΊ
The methods of fault-tolerant coding are often used in the designing of reliable and safety components of automatic control systems: both in the data transmission between system nodes, and at the level of hardware and software architecture.
The redundant coding is widely used in the management of combinational logic devices control. In this case, codes, which are oriented to the error detection rather than correction of this, are in use. Such features of codes make it possible to implement the checkable automation systems with acceptable redundancy, which does not exceed the redundancy in the situation of duplication using.
The paper highlights the method of the synthesis of self-checking combinational devices, which makes it possible to take into account the features of the source devices architecture, as well as the properties of error detection by redundant codes in solving the problem of the synthesis of technical means for diagnosis. The paper gives the basic information on the theory of the checkable digital systems synthesis on the basis of redundant codes with summation.
The basic stages of the analysis of the diagnosis objects topologies are determined with the selection of groups of outputs β groups of structurally and functionally symmetrically independent devices outputs. The formulas are given to determine the presence or the absence of a symmetrical dependence of the diagnosis object outputs. The example illustrating the calculation process is given. The main stages of the analysis of the redundant codes application in the error detection on the functionally symmetric dependent outputs are formulated. The algorithm of the synthesis of the self-checking combinational devices with taking into account the object of diagnosis structure features and the redundant codes properties is proposed.ΠΡΠΈ ΡΠΎΠ·Π΄Π°Π½ΠΈΠΈ Π½Π°Π΄Π΅ΠΆΠ½ΡΡ
ΠΈ Π±Π΅Π·ΠΎΠΏΠ°ΡΠ½ΡΡ
ΠΊΠΎΠΌΠΏΠΎΠ½Π΅Π½ΡΠΎΠ² ΡΠΈΡΡΠ΅ΠΌ Π°Π²ΡΠΎΠΌΠ°ΡΠΈΡΠ΅ΡΠΊΠΎΠ³ΠΎ ΡΠΏΡΠ°Π²Π»Π΅Π½ΠΈΡ ΡΠ°ΡΡΠΎ ΠΈΡΠΏΠΎΠ»ΡΠ·ΡΡΡΡΡ ΠΌΠ΅ΡΠΎΠ΄Ρ ΠΏΠΎΠΌΠ΅Ρ
ΠΎΡΡΡΠΎΠΉΡΠΈΠ²ΠΎΠ³ΠΎ ΠΊΠΎΠ΄ΠΈΡΠΎΠ²Π°Π½ΠΈΡ β ΠΊΠ°ΠΊ ΠΏΡΠΈ ΠΏΠ΅ΡΠ΅Π΄Π°ΡΠ΅ Π΄Π°Π½Π½ΡΡ
ΠΌΠ΅ΠΆΠ΄Ρ ΡΠ·Π»Π°ΠΌΠΈ ΡΠΈΡΡΠ΅ΠΌΡ, ΡΠ°ΠΊ ΠΈ Π½Π° ΡΡΠΎΠ²Π½Π΅ Π°ΡΡ
ΠΈΡΠ΅ΠΊΡΡΡΡ Π°ΠΏΠΏΠ°ΡΠ°ΡΠ½ΡΡ
ΠΈ ΠΏΡΠΎΠ³ΡΠ°ΠΌΠΌΠ½ΡΡ
ΡΡΠ΅Π΄ΡΡΠ². Π¨ΠΈΡΠΎΠΊΠΎ ΠΏΡΠΈΠΌΠ΅Π½ΡΠ΅ΡΡΡ ΠΈΠ·Π±ΡΡΠΎΡΠ½ΠΎΠ΅ ΠΊΠΎΠ΄ΠΈΡΠΎΠ²Π°Π½ΠΈΠ΅ ΠΏΡΠΈ ΠΎΡΠ³Π°Π½ΠΈΠ·Π°ΡΠΈΠΈ ΠΊΠΎΠ½ΡΡΠΎΠ»Ρ ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΎΠ½Π½ΡΡ
Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΈΡ
ΡΡΡΡΠΎΠΉΡΡΠ². ΠΡΠΈ ΡΡΠΎΠΌ ΠΈΡΠΏΠΎΠ»ΡΠ·ΡΡΡΡΡ ΠΊΠΎΠ΄Ρ, ΠΎΡΠΈΠ΅Π½ΡΠΈΡΠΎΠ²Π°Π½Π½ΡΠ΅ ΠΈΠΌΠ΅Π½Π½ΠΎ Π½Π° ΠΎΠ±Π½Π°ΡΡΠΆΠ΅Π½ΠΈΠ΅, Π° Π½Π΅ ΠΈΡΠΏΡΠ°Π²Π»Π΅Π½ΠΈΠ΅ ΠΎΡΠΈΠ±ΠΎΠΊ. Π’Π°ΠΊΠΈΠ΅ ΠΎΡΠΎΠ±Π΅Π½Π½ΠΎΡΡΠΈ ΠΊΠΎΠ΄ΠΎΠ² ΠΏΠΎΠ·Π²ΠΎΠ»ΡΡΡ ΡΠ΅Π°Π»ΠΈΠ·ΠΎΠ²ΡΠ²Π°ΡΡ ΠΊΠΎΠ½ΡΡΠΎΠ»Π΅ΠΏΡΠΈΠ³ΠΎΠ΄Π½ΡΠ΅ ΡΠΈΡΡΠ΅ΠΌΡ Π°Π²ΡΠΎΠΌΠ°ΡΠΈΠΊΠΈ Ρ ΠΏΡΠΈΠ΅ΠΌΠ»Π΅ΠΌΠΎΠΉ ΠΈΠ·Π±ΡΡΠΎΡΠ½ΠΎΡΡΡΡ, Π½Π΅ ΠΏΡΠ΅Π²ΡΡΠ°ΡΡΠ΅ΠΉ ΠΈΠ·Π±ΡΡΠΎΡΠ½ΠΎΡΡΠΈ ΠΏΡΠΈ ΠΈΡΠΏΠΎΠ»ΡΠ·ΠΎΠ²Π°Π½ΠΈΠΈ Π΄ΡΠ±Π»ΠΈΡΠΎΠ²Π°Π½ΠΈΡ. Π ΡΡΠ°ΡΡΠ΅ ΠΎΡΠ²Π΅ΡΠ°Π΅ΡΡΡ ΠΌΠ΅ΡΠΎΠ΄ ΡΠΈΠ½ΡΠ΅Π·Π° ΡΠ°ΠΌΠΎΠΏΡΠΎΠ²Π΅ΡΡΠ΅ΠΌΡΡ
ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΎΠ½Π½ΡΡ
ΡΡΡΡΠΎΠΉΡΡΠ², ΠΏΠΎΠ·Π²ΠΎΠ»ΡΡΡΠΈΠΉ ΡΡΠΈΡΡΠ²Π°ΡΡ ΠΏΡΠΈ ΡΠ΅ΡΠ΅Π½ΠΈΠΈ Π·Π°Π΄Π°ΡΠΈ ΡΠΈΠ½ΡΠ΅Π·Π° ΡΠ΅Ρ
Π½ΠΈΡΠ΅ΡΠΊΠΈΡ
ΡΡΠ΅Π΄ΡΡΠ² Π΄ΠΈΠ°Π³Π½ΠΎΡΡΠΈΡΠΎΠ²Π°Π½ΠΈΡ ΠΎΡΠΎΠ±Π΅Π½Π½ΠΎΡΡΠΈ Π°ΡΡ
ΠΈΡΠ΅ΠΊΡΡΡΡ ΠΈΡΡ
ΠΎΠ΄Π½ΡΡ
ΡΡΡΡΠΎΠΉΡΡΠ², Π° ΡΠ°ΠΊΠΆΠ΅ ΡΠ²ΠΎΠΉΡΡΠ²Π° ΠΎΠ±Π½Π°ΡΡΠΆΠ΅Π½ΠΈΡ ΠΎΡΠΈΠ±ΠΎΠΊ ΠΈΠ·Π±ΡΡΠΎΡΠ½ΡΠΌΠΈ ΠΊΠΎΠ΄Π°ΠΌΠΈ. ΠΠ°ΡΡΡΡ Π±Π°Π·ΠΎΠ²ΡΠ΅ ΡΠ²Π΅Π΄Π΅Π½ΠΈΡ ΠΈΠ· ΡΠ΅ΠΎΡΠΈΠΈ ΡΠΈΠ½ΡΠ΅Π·Π° ΠΊΠΎΠ½ΡΡΠΎΠ»Π΅ΠΏΡΠΈΠ³ΠΎΠ΄Π½ΡΡ
Π΄ΠΈΡΠΊΡΠ΅ΡΠ½ΡΡ
ΡΠΈΡΡΠ΅ΠΌ Π½Π° ΠΎΡΠ½ΠΎΠ²Π΅ ΠΈΠ·Π±ΡΡΠΎΡΠ½ΡΡ
ΠΊΠΎΠ΄ΠΎΠ² Ρ ΡΡΠΌΠΌΠΈΡΠΎΠ²Π°Π½ΠΈΠ΅ΠΌ. ΠΠΏΡΠ΅Π΄Π΅Π»Π΅Π½Ρ ΠΊΠ»ΡΡΠ΅Π²ΡΠ΅ ΡΡΠ°ΠΏΡ Π°Π½Π°Π»ΠΈΠ·Π° ΡΠΎΠΏΠΎΠ»ΠΎΠ³ΠΈΠΉ ΠΎΠ±ΡΠ΅ΠΊΡΠΎΠ² Π΄ΠΈΠ°Π³Π½ΠΎΡΡΠΈΡΠΎΠ²Π°Π½ΠΈΡ Ρ Π²ΡΠ΄Π΅Π»Π΅Π½ΠΈΠ΅ΠΌ ΡΠΏΠ΅ΡΠΈΠ°Π»ΡΠ½ΡΡ
Π³ΡΡΠΏΠΏ Π²ΡΡ
ΠΎΠ΄ΠΎΠ² β Π³ΡΡΠΏΠΏ ΡΡΡΡΠΊΡΡΡΠ½ΠΎ ΠΈ ΡΡΠ½ΠΊΡΠΈΠΎΠ½Π°Π»ΡΠ½ΠΎ ΡΠΈΠΌΠΌΠ΅ΡΡΠΈΡΠ½ΠΎ Π½Π΅Π·Π°Π²ΠΈΡΠΈΠΌΡΡ
Π²ΡΡ
ΠΎΠ΄ΠΎΠ² ΡΡΡΡΠΎΠΉΡΡΠ². ΠΡΠΈΠ²ΠΎΠ΄ΡΡΡΡ ΡΠΎΡΠΌΡΠ»Ρ, ΠΏΠΎΠ·Π²ΠΎΠ»ΡΡΡΠΈΠ΅ ΡΡΡΠ°Π½ΠΎΠ²ΠΈΡΡ Π½Π°Π»ΠΈΡΠΈΠ΅ ΠΈΠ»ΠΈ ΠΎΡΡΡΡΡΡΠ²ΠΈΠ΅ ΡΠΈΠΌΠΌΠ΅ΡΡΠΈΡΠ½ΠΎΠΉ Π·Π°Π²ΠΈΡΠΈΠΌΠΎΡΡΠΈ Π²ΡΡ
ΠΎΠ΄ΠΎΠ² ΠΎΠ±ΡΠ΅ΠΊΡΠ° Π΄ΠΈΠ°Π³Π½ΠΎΡΡΠΈΡΠΎΠ²Π°Π½ΠΈΡ. ΠΠ°Π΅ΡΡΡ ΠΏΡΠΈΠΌΠ΅Ρ, ΠΈΠ»Π»ΡΡΡΡΠΈΡΡΡΡΠΈΠΉ ΠΏΡΠΎΡΠ΅ΡΡ Π²ΡΡΠΈΡΠ»Π΅Π½ΠΈΠΉ. Π‘ΡΠΎΡΠΌΡΠ»ΠΈΡΠΎΠ²Π°Π½Ρ ΠΎΡΠ½ΠΎΠ²Π½ΡΠ΅ ΡΡΠ°ΠΏΡ Π°Π½Π°Π»ΠΈΠ·Π° ΠΏΡΠΈΠΌΠ΅Π½Π΅Π½ΠΈΡ ΠΈΠ·Π±ΡΡΠΎΡΠ½ΡΡ
ΠΊΠΎΠ΄ΠΎΠ² ΠΏΡΠΈ Π²ΡΡΠ²Π»Π΅Π½ΠΈΠΈ ΠΎΡΠΈΠ±ΠΎΠΊ Π½Π° ΡΡΠ½ΠΊΡΠΈΠΎΠ½Π°Π»ΡΠ½ΠΎ ΡΠΈΠΌΠΌΠ΅ΡΡΠΈΡΠ½ΠΎ Π·Π°Π²ΠΈΡΠΈΠΌΡΡ
Π²ΡΡ
ΠΎΠ΄Π°Ρ
. ΠΠ°Π½ Π°Π»Π³ΠΎΡΠΈΡΠΌ ΡΠΈΠ½ΡΠ΅Π·Π° ΡΠ°ΠΌΠΎΠΏΡΠΎΠ²Π΅ΡΡΠ΅ΠΌΡΡ
Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΈΡ
ΡΡΡΡΠΎΠΉΡΡΠ² Ρ ΡΡΠ΅ΡΠΎΠΌ ΠΎΡΠΎΠ±Π΅Π½Π½ΠΎΡΡΠ΅ΠΉ ΡΡΡΡΠΊΡΡΡΡ ΠΎΠ±ΡΠ΅ΠΊΡΠ° Π΄ΠΈΠ°Π³Π½ΠΎΡΡΠΈΡΠΎΠ²Π°Π½ΠΈΡ ΠΈ ΡΠ²ΠΎΠΉΡΡΠ² ΠΈΠ·Π±ΡΡΠΎΡΠ½ΡΡ
ΠΊΠΎΠ΄ΠΎΠ²
Π‘ΠΏΠΎΡΠΎΠ± ΠΏΠΎΡΡΡΠΎΠ΅Π½ΠΈΡ ΡΠ΅ΠΌΠ΅ΠΉΡΡΠ²Π° ΠΊΠΎΠ΄ΠΎΠ² Ρ ΡΡΠΌΠΌΠΈΡΠΎΠ²Π°Π½ΠΈΠ΅ΠΌ Ρ Π½Π°ΠΈΠΌΠ΅Π½ΡΡΠΈΠΌ ΠΎΠ±ΡΠΈΠΌ ΠΊΠΎΠ»ΠΈΡΠ΅ΡΡΠ²ΠΎΠΌ Π½Π΅ΠΎΠ±Π½Π°ΡΡΠΆΠΈΠ²Π°Π΅ΠΌΡΡ ΠΎΡΠΈΠ±ΠΎΠΊ Π² ΠΈΠ½ΡΠΎΡΠΌΠ°ΡΠΈΠΎΠ½Π½ΡΡ Π²Π΅ΠΊΡΠΎΡΠ°Ρ
The research results of the methods for formation of separable sum codes with the minimum number of undetectable errors in data vectors are presented. A formula for counting the number of undetectable errors in data vectors and codes family properties are given. A universal method for formation of such codes is shown, which makes it possible for each value of the data vector length to obtain a whole family of codes that also have different distributions of undetectable errors by type and multiplicity. An example of codes formation, methods for analyzing characteristics, code comparison are presented. A method for synthesizing coders of developed sum codes is suggested.Β ΠΠ·Π»ΠΎΠΆΠ΅Π½Ρ ΡΠ΅Π·ΡΠ»ΡΡΠ°ΡΡ ΠΈΡΡΠ»Π΅Π΄ΠΎΠ²Π°Π½ΠΈΠΉ ΡΠΏΠΎΡΠΎΠ±ΠΎΠ² ΠΏΠΎΡΡΡΠΎΠ΅Π½ΠΈΡ ΡΠ°Π·Π΄Π΅Π»ΠΈΠΌΡΡ
ΠΊΠΎΠ΄ΠΎΠ² Ρ ΡΡΠΌΠΌΠΈΡΠΎΠ²Π°Π½ΠΈΠ΅ΠΌ Ρ Π½Π°ΠΈΠΌΠ΅Π½ΡΡΠΈΠΌ ΠΎΠ±ΡΠΈΠΌ ΠΊΠΎΠ»ΠΈΡΠ΅ΡΡΠ²ΠΎΠΌ Π½Π΅ΠΎΠ±Π½Π°ΡΡΠΆΠΈΠ²Π°Π΅ΠΌΡΡ
ΠΎΡΠΈΠ±ΠΎΠΊ Π² ΠΈΠ½ΡΠΎΡΠΌΠ°ΡΠΈΠΎΠ½Π½ΡΡ
Π²Π΅ΠΊΡΠΎΡΠ°Ρ
. ΠΡΠΈΠ²Π΅Π΄Π΅Π½Ρ ΡΠΎΡΠΌΡΠ»Ρ ΠΏΠΎΠ΄ΡΡΠ΅ΡΠ° ΡΠΈΡΠ»Π° Π½Π΅ΠΎΠ±Π½Π°ΡΡΠΆΠΈΠ²Π°Π΅ΠΌΡΡ
ΠΎΡΠΈΠ±ΠΎΠΊ Π² ΠΈΠ½ΡΠΎΡΠΌΠ°ΡΠΈΠΎΠ½Π½ΡΡ
Π²Π΅ΠΊΡΠΎΡΠ°Ρ
ΠΈ ΡΠ²ΠΎΠΉΡΡΠ²Π° Π΄Π°Π½Π½ΠΎΠ³ΠΎ ΠΊΠ»Π°ΡΡΠ° ΠΊΠΎΠ΄ΠΎΠ². ΠΡΠ΅Π΄ΡΡΠ°Π²Π»Π΅Π½ ΡΠ½ΠΈΠ²Π΅ΡΡΠ°Π»ΡΠ½ΡΠΉ ΡΠΏΠΎΡΠΎΠ± ΠΏΠΎΡΡΡΠΎΠ΅Π½ΠΈΡ ΡΠ°ΠΊΠΈΡ
ΠΊΠΎΠ΄ΠΎΠ², Π΄Π°ΡΡΠΈΠΉ Π΄Π»Ρ ΠΊΠ°ΠΆΠ΄ΠΎΠ³ΠΎ Π·Π½Π°ΡΠ΅Π½ΠΈΡ Π΄Π»ΠΈΠ½Ρ ΠΈΠ½ΡΠΎΡΠΌΠ°ΡΠΈΠΎΠ½Π½ΠΎΠ³ΠΎ Π²Π΅ΠΊΡΠΎΡΠ° Π²ΠΎΠ·ΠΌΠΎΠΆΠ½ΠΎΡΡΡ ΠΏΠΎΠ»ΡΡΠ΅Π½ΠΈΡ ΡΠ΅Π»ΠΎΠ³ΠΎ ΡΠ΅ΠΌΠ΅ΠΉΡΡΠ²Π° ΠΊΠΎΠ΄ΠΎΠ², ΠΎΠ±Π»Π°Π΄Π°ΡΡΠΈΡ
ΠΊ ΡΠΎΠΌΡ ΠΆΠ΅ ΡΠ°Π·Π»ΠΈΡΠ½ΡΠΌΠΈ ΡΠ°ΡΠΏΡΠ΅Π΄Π΅Π»Π΅Π½ΠΈΡΠΌΠΈ Π½Π΅ΠΎΠ±Π½Π°ΡΡΠΆΠΈΠ²Π°Π΅ΠΌΡΡ
ΠΎΡΠΈΠ±ΠΎΠΊ ΠΏΠΎ Π²ΠΈΠ΄Π°ΠΌ ΠΈ ΠΊΡΠ°ΡΠ½ΠΎΡΡΡΠΌ. ΠΡΠΈΠ²Π΅Π΄Π΅Π½Ρ ΠΏΡΠΈΠΌΠ΅ΡΡ ΠΏΠΎΡΡΡΠΎΠ΅Π½ΠΈΡ ΠΊΠΎΠ΄ΠΎΠ², ΠΌΠ΅ΡΠΎΠ΄ΠΎΠ»ΠΎΠ³ΠΈΡ Π°Π½Π°Π»ΠΈΠ·Π° ΠΈΡ
Ρ
Π°ΡΠ°ΠΊΡΠ΅ΡΠΈΡΡΠΈΠΊ, Π° ΡΠ°ΠΊΠΆΠ΅ Π΄Π°Π½ΠΎ ΡΡΠ°Π²Π½Π΅Π½ΠΈΠ΅ ΠΊΠΎΠ΄ΠΎΠ² ΠΌΠ΅ΠΆΠ΄Ρ ΡΠΎΠ±ΠΎΠΉ. ΠΡΠ΅Π΄Π»ΠΎΠΆΠ΅Π½ ΠΌΠ΅ΡΠΎΠ΄ ΡΠΈΠ½ΡΠ΅Π·Π° ΠΊΠΎΠ΄Π΅ΡΠΎΠ² ΡΠ°Π·ΡΠ°Π±ΠΎΡΠ°Π½Π½ΡΡ
ΠΊΠΎΠ΄ΠΎΠ² Ρ ΡΡΠΌΠΌΠΈΡΠΎΠ²Π°Π½ΠΈΠ΅ΠΌ
Introduction to Logic Circuits & Logic Design with Verilog
The overall goal of this book is to fill a void that has appeared in the instruction of digital circuits over
the past decade due to the rapid abstraction of system design. Up until the mid-1980s, digital circuits
were designed using classical techniques. Classical techniques relied heavily on manual design
practices for the synthesis, minimization, and interfacing of digital systems. Corresponding to this design
style, academic textbooks were developed that taught classical digital design techniques. Around 1990,
large-scale digital systems began being designed using hardware description languages (HDL) and
automated synthesis tools. Broad-scale adoption of this modern design approach spread through the
industry during this decade. Around 2000, hardware description languages and the modern digital
design approach began to be taught in universities, mainly at the senior and graduate level. There
were a variety of reasons that the modern digital design approach did not penetrate the lower levels of
academia during this time. First, the design and simulation tools were difficult to use and overwhelmed
freshman and sophomore students. Second, the ability to implement the designs in a laboratory setting
was infeasible. The modern design tools at the time were targeted at custom integrated circuits, which
are cost- and time-prohibitive to implement in a university setting. Between 2000 and 2005, rapid
advances in programmable logic and design tools allowed the modern digital design approach to be
implemented in a university setting, even in lower-level courses. This allowed students to learn the
modern design approach based on HDLs and prototype their designs in real hardware, mainly fieldprogrammable gate arrays (FPGAs). This spurred an abundance of textbooks to be authored, teaching
hardware description languages and higher levels of design abstraction. This trend has continued until
today. While abstraction is a critical tool for engineering design, the rapid movement toward teaching only
the modern digital design techniques has left a void for freshman- and sophomore-level courses in digital
circuitry. Legacy textbooks that teach the classical design approach are outdated and do not contain
sufficient coverage of HDLs to prepare the students for follow-on classes. Newer textbooks that teach
the modern digital design approach move immediately into high-level behavioral modeling with minimal
or no coverage of the underlying hardware used to implement the systems. As a result, students are not
being provided the resources to understand the fundamental hardware theory that lies beneath the
modern abstraction such as interfacing, gate-level implementation, and technology optimization.
Students moving too rapidly into high levels of abstraction have little understanding of what is going
on when they click the βcompile and synthesizeβ button of their design tool. This leads to graduates who
can model a breadth of different systems in an HDL but have no depth into how the system is
implemented in hardware. This becomes problematic when an issue arises in a real design and there
is no foundational knowledge for the students to fall back on in order to debug the problem
- β¦