Variation Resilient Adaptive Controller for Subthreshold Circuits

Subthreshold logic is showing good promise as a viable ultra-low-power circuit design technique for power-limited applications. For this design technique to gain widespread adoption, one of the most pressing concerns is how to improve the robustness of subthreshold logic to process and temperature variations. We propose a variation resilient adaptive controller for subthreshold circuits with the following novel features: new sensor based on time-to-digital converter for capturing the variations accurately as digital signatures, and an all-digital DC-DC converter incorporating the sensor capable of generating an operating operating Vdd from 0V to 1.2V with a resolution of 18.75mV, suitable for subthreshold circuit operation. The benefits of the proposed controller is reflected with energy improvement of up to 55% compared to when no controller is employed. The detailed implementation and validation of the proposed controller is discussed

Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines

Large-capacity Content Addressable Memory (CAM) is a key element in a wide variety of applications. The inevitable complexities of scaling MOS transistors introduce a major challenge in the realization of such systems. Convergence of disparate technologies, which are compatible with CMOS processing, may allow extension of Moore's Law for a few more years. This paper provides a new approach towards the design and modeling of Memristor (Memory resistor) based Content Addressable Memory (MCAM) using a combination of memristor MOS devices to form the core of a memory/compare logic cell that forms the building block of the CAM architecture. The non-volatile characteristic and the nanoscale geometry together with compatibility of the memristor with CMOS processing technology increases the packing density, provides for new approaches towards power management through disabling CAM blocks without loss of stored data, reduces power dissipation, and has scope for speed improvement as the technology matures.Comment: 10 pages, 11 figure

Subthreshold circuits: Design, implementation and application

Digital circuits operating in the subthreshold region of the transistor are being used as an ideal option for ultra low power complementary metal-oxide-semiconductor (CMOS) design. The use of subthreshold circuit design in cryptographic systems is gaining importance as a counter measure to power analysis attacks. A power analysis attack is a non-invasive side channel attack in which the power consumption of the cryptographic system can be analyzed to retrieve the encrypted data. A number of techniques to increase the resistance to power attacks have been proposed at algorithmic and hardware levels, but these techniques suffer from large area and power overheads. The main aim of this research is to understand the viability of implementing subthreshold systems for cryptographic applications. Standard cell libraries in subthreshold are designed and a methodology to identify the minimum energy point, aspect ratio, frequency range and operating voltage for CMOS standard cells is defined. As scalar multiplication is the fundamental operation in elliptic curve cryptographic systems, a digit-level gaussian normal basis (GNB) multiplier is implemented using the aforementioned standard cells. A similar standard-cell library is designed for the multiplier to operate in the superthreshold regime. The subthreshold and superthreshold multipliers are then subjected to a differential power analysis attack. Power performance and signal-to-noise ratio (SNR) of both these systems are compared to evaluate the usefulness of the subthreshold design. The power consumption of the subthreshold multiplier is 4.554 uW, the speed of the multiplier is 65.1 KHz and the SNR is 40 dB. The superthreshold multiplier has a power consumption of 4.005 mW, the speed of the multiplier is 330 MHz and the SNR is 200 dB. Reduced power consumption, hence reduced SNR, increases the resistance of the subthreshold multiplier against power analysis attacks. (Refer to PDF for exact formulas)

Ultra-Low Power Circuit Design for Cubic-Millimeter Wireless Sensor Platform.

Modern daily life is surrounded by smaller and smaller computing devices. As Bell’s Law predicts, the research community is now looking at tiny computing platforms and mm3-scale sensor systems are drawing an increasing amount of attention since they can create a whole new computing environment. Designing mm3-scale sensor nodes raises various circuit and system level challenges and we have addressed and proposed novel solutions for many of these challenges to create the first complete 1.0mm3 sensor system including a commercial microprocessor. We demonstrate a 1.0mm3 form factor sensor whose modular die-stacked structure allows maximum volume utilization. Low power I2C communication enables inter-layer serial communication without losing compatibility to standard I2C communication protocol. A dual microprocessor enables concurrent computation for the sensor node control and measurement data processing. A multi-modal power management unit allowed energy harvesting from various harvesting sources. An optical communication scheme is provided for initial programming, synchronization and re-programming after recovery from battery discharge. Standby power reduction techniques are investigated and a super cut-off power gating scheme with an ultra-low power charge pump reduces the standby power of logic circuits by 2-19× and memory by 30%. Different approaches for designing low-power memory for mm3-scale sensor nodes are also presented in this work. A dual threshold voltage gain cell eDRAM design achieves the lowest eDRAM retention power and a 7T SRAM design based on hetero-junction tunneling transistors reduces the standby power of SRAM by 9-19× with only 15% area overhead. We have paid special attention to the timer for the mm3-scale sensor systems and propose a multi-stage gate-leakage-based timer to limit the standard deviation of the error in hourly measurement to 196ms and a temperature compensation scheme reduces temperature dependency to 31ppm/°C. These techniques for designing ultra-low power circuits for a mm3-scale sensor enable implementation of a 1.0mm3 sensor node, which can be used as a skeleton for future micro-sensor systems in variety of applications. These microsystems imply the continuation of the Bell’s Law, which also predicts the massive deployment of mm3-scale computing systems and emergence of even smaller and more powerful computing systems in the near future.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/91438/1/sori_1.pd

Design of a process monitor and of peripheral circuits enabling the characterisation of CMOS 45nm Ultra Low Power and Litho Friendly optimised standard cells

L’evoluzione della tecnologia CMOS è caratterizzata dallo scaling delle dimensioni dei dispositivi e dalla riduzione del consumo di potenza. Dal momento che le difficoltà di realizzazione aumentano al diminuire delle dimensioni, nei nodi tecnologici più recenti la velocità del processo di scaling sta diminuendo. Uno dei maggiori problemi causati dalla riduzione delle dimensioni dei dispositivi è la variabilità del processo di fabbricazione. L’obiettivo di questo progetto è quello di ridurre gli effetti che la variabilità del processo di realizzazione nel nodo tecnologico CMOS 45 nm ha sulle prestazioni della logica digitale, grazie a metodi di design non convenzionali. In questo progetto è stato realizzato un testchip per studiare e quantificare i vantaggi, in termini di prestazioni, ottenuti tramite la progettazione di librerie standard-like ottimizzate secondo canoni di litho-friendliness (LF) e ultra low power (ULP). Le standard cells LF utilizzano layout estremamente regolari. Le standard cells ULP sono progettate per operare con tensioni di alimentazioni notevolmente ridotte. Il fine principale del testchip sta nell’ottenere una panoramica della variabilità locale e globale di parametri significativi nella progettazione digitale: ad esempio la frequenza di lavoro e il consumo di potenza. Inoltre, nel testchip sono stati realizzati alcuni circuiti originali per il monitoraggio della qualità del processo di fabbricazione. The evolution of the CMOS technology is characterized by the scaling of transistors size and by the reduction of their power dissipation. In the last technology nodes the speed of the scaling process is decreasing, since the complexity of the technology increases with its size reduction. One of the main issues caused by the shrinking of the transistor size is the variability of the fabrication process. The target of this project is to reduce the effects of the variability of the realisation process in a CMOS 45 nm technology node in digital circuits performances, using unconventional design methods. A testchip is realised in this project to investigate and to quantify the improvement of the circuit performances obtained through the design of dedicated litho-friendly (LF) and of the Ultra Low Power (ULP) standard-like libraries. The LF standard cells libraries are optimised for lithography using ultra regular layout styles. The ULP standard cells library is optimised to operate at extremely low supply voltage. The main aim of the testchip is to get insight into the local and the global variability of relevant parameters for digital design, such as operating frequency and power consumption. In this testchip some structures are also included, to develop some innovative circuits that should help to monitor the quality of the technology process

LPSR: Novel Low Power State Retention Technique for CMOS VLSI Design

In mobile computing and mobile communication applications powered by battery, the battery life is a premier concern. Leakage power loss is critical in CMOS VLSI circuits as it leaks the battery even when devices are in idle state. To reduce subthreshold leakage power as well as total power in CMOS logic gates and circuits a new circuit technique called LPSR Technique is proposed in this work. Earlier well known techniques for leakage reduction and state retention are compared with this technique. This technique reduces maximum amount of leakage power during deep sleep mode, maximum power reduction during dynamic (clocked) mode and has a provision of preserving state in low power sleep mode. All the circuits are designed, simulated and low power performance evaluation is done using 90nm CMOS technology files in Cadence Design Environmen

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

The design of low-power SRAM cell becomes a necessity in today\u27s FPGAs, because SRAM is a critical component in FPGA design and consumes a large fraction of the total power. The present chapter provides an overview of various factors responsible for power consumption in FPGA and discusses the design techniques of low-power SRAM-based FPGA at system level, device level, and architecture levels. Finally, the chapter proposes a data-aware dynamic SRAM cell to control the power consumption in the cell. Stack effect has been adopted in the design to reduce the leakage current. The various peripheral circuits like address decoder circuit, write/read enable circuits, and sense amplifier have been modified to implement a power-efficient SRAM-based FPGA