2 research outputs found
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Low voltage techniques for pipelined analog-to-digital converters
To realize pipelined ADCs in deep-submicron processes, low voltage techniques
must be developed to work around problems created by limited supply voltages such as
the floating switch dead zone, reduced SNR, and reduced OpAmp performance.
This thesis analyzes standard and low voltage design issues for pipelined ADCs
and proposes a fully-differential implementation of the OpAmp Reset Switching
Technique (ORST) as a suitable low voltage design solution. The technique uses a true
fully differential MDAC structure with a switching common-mode feedback to achieve
increased linearity and noise performance over the previously published ORST.
A pipelined ADC test chip is designed to implement the fully differential ORST
technique as a proof of concept. The design also includes a simple, low power input
sampling network that also allows an increased input signal range and saves power by
removing the dedicated, front-end S/H.
Prototype performance demonstrates the fully differential ORST and shows
sampling speeds of up to 60 MS/s, 51.4 dB SNR, 58.8 dB SFDR, and 49.7 dB SNDR for
an 8-bit ENOB in a 0.18 μm CMOS process with a 1 V supply. Little change in distortion
is observed up to 90 MHz input frequency, demonstrating operation without a S/H
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Correlated level shifting as a power-saving method to reduce the effects of finite DC gain and signal swing in opamps
This thesis presents methods to reduce the effects of finite opamp DC gain, output voltage swing limitations in opamps, and component mismatches. The primary contribution of this thesis is a new switched-capacitor method named correlated level shifting (CLS). CLS enables true rail-to-rail operation by storing an estimate of the desired signal on a capacitor during an "estimate" phase, and subtracting the signal from the active circuitry (typically an opamp) during a "level shift" phase. This is done within the confines of a feedback loop. The effective loop-gain is the product of the loop-gains during the estimate and level shift phases. This enables, for example, a two-stage opamp to have the accuracy of a four-stage opamp. It also enables full utilization of the power supply since the gain block's output voltage can exceed the power supply. The thesis shows that the full utilization of the power supply and the increased DC effective loop gain leads to a significant power savings compared to existing techniques.
The methods are presented in the context of pipelined analog-to-digital converters, although the methods can be used with other circuits that use opamps or are sensitive to component mismatch. An overview of the detrimental effects of reduced signal swing and low DC gain is given with an emphasis on the cost in power to correct these deficiencies when limited to existing circuit techniques. CLS is then shown to correct these deficiencies without increasing power. A detailed explanation of CLS operation is given, as are measured results from a 12-bit pipelined analog-to-digital converter that was fabricated using a 0.18μ CMOS process. The results include greater than 10-bit performance with true rail-to-rail operation.
An overview of calibration is also given and the limitations are discussed. An argument is made that using CLS in addition to calibration will reduce power by increasing signal-to-noise ratio and reducing and linearizing the errors due to finite opamp gain. In addition, a method to reduce the effects of mismatch by measuring the relative size of elements is presented.
Finally, several avenues for future research into CLS are given