4 research outputs found
FPGA Implementation of Channel Mismatch Calibration in TIADCs for Signals in Any Nyquist Bands
This paper presents a fully digital background calibration technique of the gain and timing mismatches in undersampling Time-Interleaved Analog-to-Digital Converters for the wideband bandlimited input signal at any Nyquist bands. The proposed technique does not require an additional reference channel nor a pilot input. The channel mismatch parameters are estimated based on the mismatch frequency band. The experimental results shows the efficiency of the proposed mitigation technique with the SNDR improvement of 16dB for 4-channel 60dB SNR TIADC clocked at 2.7GHz given a multi-tone input occupied at the third Nyquist band. The hardware architecture of the proposed technique is designed and validated on Altera FPGA DE4 board. The synthesized design utilizes a very little amount of the hardware resource in the FPGA chip and works correctly on a Hardware-In-the-Loop emulation framework
Estimation and Calibration Algorithms for Distributed Sampling Systems
Thesis Supervisor: Gregory W. Wornell
Title: Professor of Electrical Engineering and Computer ScienceTraditionally, the sampling of a signal is performed using a single component such as an
analog-to-digital converter. However, many new technologies are motivating the use of
multiple sampling components to capture a signal. In some cases such as sensor networks,
multiple components are naturally found in the physical layout; while in other cases like
time-interleaved analog-to-digital converters, additional components are added to increase
the sampling rate. Although distributing the sampling load across multiple channels can
provide large benefits in terms of speed, power, and resolution, a variety mismatch errors
arise that require calibration in order to prevent a degradation in system performance.
In this thesis, we develop low-complexity, blind algorithms for the calibration of distributed
sampling systems. In particular, we focus on recovery from timing skews that
cause deviations from uniform timing. Methods for bandlimited input reconstruction from
nonuniform recurrent samples are presented for both the small-mismatch and the low-SNR
domains. Alternate iterative reconstruction methods are developed to give insight into the
geometry of the problem.
From these reconstruction methods, we develop time-skew estimation algorithms that
have high performance and low complexity even for large numbers of components. We also
extend these algorithms to compensate for gain mismatch between sampling components.
To understand the feasibility of implementation, analysis is also presented for a sequential
implementation of the estimation algorithm.
In distributed sampling systems, the minimum input reconstruction error is dependent
upon the number of sampling components as well as the sample times of the components. We
develop bounds on the expected reconstruction error when the time-skews are distributed
uniformly. Performance is compared to systems where input measurements are made via
projections onto random bases, an alternative to the sinc basis of time-domain sampling.
From these results, we provide a framework on which to compare the effectiveness of any
calibration algorithm.
Finally, we address the topic of extreme oversampling, which pertains to systems with
large amounts of oversampling due to redundant sampling components. Calibration algorithms
are developed for ordering the components and for estimating the input from ordered
components. The algorithms exploit the extra samples in the system to increase estimation
performance and decrease computational complexity
Post Conversion Correction of Non-Linear Mismatches for Time Interleaved Analog-to-Digital Converters
Time Interleaved Analog-to-Digital Converters (TI-ADCs) utilize an architecture which enables conversion rates well beyond the capabilities of a single converter while preserving most or all of the other performance characteristics of the converters on which said architecture is based. Most of the approaches discussed here are independent of architecture; some solutions take advantage of specific architectures. Chapter 1 provides the problem formulation and reviews the errors found in ADCs as well as a brief literature review of available TI-ADC error correction solutions. Chapter 2 presents the methods and materials used in implementation as well as extend the state of the art for post conversion correction. Chapter 3 presents the simulation results of this work and Chapter 4 concludes the work. The contribution of this research is three fold: A new behavioral model was developed in SimulinkTM and MATLABTM to model and test linear and nonlinear mismatch errors emulating the performance data of actual converters. The details of this model are presented as well as the results of cumulant statistical calculations of the mismatch errors which is followed by the detailed explanation and performance evaluation of the extension developed in this research effort. Leading post conversion correction methods are presented and an extension with derivations is presented. It is shown that the data converter subsystem architecture developed is capable of realizing better performance of those currently reported in the literature while having a more efficient implementation