Repairing Event Logs Using Timed Process Models

Process mining aims to infer meaningful insights from process-related data and attracted the attention of practitioners, tool-vendors, and researchers in recent years. Traditionally, event logs are assumed to describe the as-is situation. But this is not necessarily the case in environments where logging may be compromised due to manual logging. For example, hospital staff may need to manually enter information regarding the patient’s treatment. As a result, events or timestamps may be missing or incorrect. In this work, we make use of process knowledge captured in process models, and provide a method to repair missing events in the logs. This way, we facilitate analysis of incomplete logs. We realize the repair by combining stochastic Petri nets, alignments, and Bayesian networks. Keywords: process mining; missing data; stochastic Petri nets; Bayesian network

Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model

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Statistical static timing analysis considering the impact of power supply noise in VLSI circuits

As semiconductor technology is scaled and voltage level is reduced, the impact of the variation in power supply has become very significant in predicting the realistic worst-case delays in integrated circuits. The analysis of power supply noise is inevitable because high correlations exist between supply voltage and delay. Supply noise analysis has often used a vector-based timing analysis approach. Finding a set of test vectors in vector-based approaches, however, is very expensive, particularly during the design phase, and becomes intractable for larger circuits in DSM technology. In this work, two novel vectorless approaches are described such that increases in circuit delay, because of power supply noise, can be efficiently, quickly estimated. Experimental results on ISCAS89 circuits reveal the accuracy and efficiency of my approaches: in s38417 benchmark circuits, errors on circuit delay distributions are less than 2%, and both of my approaches are 67 times faster than the traditional vector-based approach. Also, the results show the importance of considering care-bits, which sensitize the longest paths during the power supply noise analysis

ZHANG et al.: SSTA WITH CORRELATIONS 1 Statistical Static Timing Analysis with Conditional Linear MAX/MIN Approximation and Extended Canonical Timing Model

An efficient and accurate statistical static timing analysis (SSTA) algorithm is reported in this work which features (a) a conditional linear approximation method of the MAX/MIN timing operator, (b) an extended canonical representation of correlated timing variables, and (c) a variation pruning method that facilitates intelligent trade-off between simulation time and accuracy of simulation result. A special design focus of the proposed algorithm is on the propagation of the statistical correlation among timing variables through the nonlinear circuit elements. The proposed algorithm distinguishes itself from existing block based SSTA algorithms in that it not only deals with correlations due to dependence on global variation factors, but also correlations due to signal propagation path reconvergence. Tested with ISCAS benchmark suites, the proposed algorithm has demonstrated very satisfactory performance in terms of both accuracy and running time. Compared with Monte Carlo based statistical timing simulation, the output probability distribution got from the proposed algorithm is within 1.5 % estimation error while a 350 times speed-up is achieved over a circuit with 5355 gates. I