The roll back chip: hardware support for distributed simulation using time warp

Journal ArticleDistributed simulation offers an attractive means of meeting the high computational demands of discrete event simulation programs. The Time Warp mechanism has been proposed to ensure correct sequencing of events in distributed simulation programs without blocking processes unnecessarily. However, the overhead of state saving and rollback in Time Warp is one obstacle that may severely degrade performance. A special purpose hardware component, the rollback chip (RBC), is proposed to manage the state of a processor and provide an efficient rollback mechanism within a node of a parallel computer. The chip may be viewed as a special purpose memory management unit that lies on the data path between processor and memory. The algorithm implemented by the rollback chip is described, as well as extensions to the basic design. Implementation of the chip is briefly discussed. In addition to distributed simulation, the rollback chip may be used in other applications using the Time Warp mechanism, notably distributed database concurrency control

Web based evaluation of material handling alternatives for automated manufacturing : a parallel replications approach.

This research project describes the application of a master/slave configuration of processors to study a comparison of alternative material handling configurations for automated manufacturing. Such a study usually requires a large number of simulation replications, and carrying out those replications on a multi-processor platform can yield a significant savings in elapsed time. The objective of this study is to develop such a platform. In the present application, a parallel replication simulation system is developed to foster simultaneous processing. This system utilizes two separate applications to facilitate communication between master and slave computers. Additionally, the master and slave or client applications work in conjunction with a specialized set of Arena(tm) simulation models. The simulation models considered in this research effort represent two types of transport mechanisms in a closed cell work environment. Transport type, transport velocity, and an associated efficiency factor of a machine in cell 3. These models have been modified for use within the parallel replications environment. This system uses 2^3 = 8 design points (simulation models) for an experimental design. The models are transferred to remote PCUs via Transmission Control Protocol (TCP) file transfer. Following receipt, the models are executed, and results sent back to the master application where factor significance is determined. The resulting Metamodel (Kleijnen, 1979) describes a linear relationship between model variables, and system output

Time warp on a shared memory multiprocessor

Journal ArticleA variation of the Time Warp parallel discrete event simulation mechanism is presented that is optimized for execution on a shared memory multiprocessor. In particular, the direct cancellation mechanism is proposed that eliminates the need for anti-messages and provides an efficient mechanism for cancelling erroneous computations. The mechanism thereby eliminates many of the overheads associated with conventional, message-based implementations of Time Warp. More importantly, this mechanism effects rapid repairs of the parallel computation when an error is discovered. Initial performance measurements of an implementation of the mechanism executing on a BBN Butterfly? multiprocessor are presented. These measurements indicate that the mechanism achieves good performance, particularly for many workloads where conservative clock synchronization algorithms perform poorly. Speedups as high as 56.8 using 64 processors were obtained. However, our studies also indicate that state saving overheads represent a significant stumbling block for many parallel simulations using Time Warp

Performance measurements of distributed simulation strategies

Journal ArticleA multiprocessor-based, distributed simulation testbed is described that facilitates controlled experimentation with distributed simulation algorithms. The performance of simulation strategies using deadlock avoidance and deadlock detection and recovery techniques are examined using various synthetic and actual workloads. The distributed simulators are compared with a uniprocessor-based event list implementation. Results of a series of experiments demonstrate that message population and the degree to which processes can look ahead in simulated time play critical roles in the performance of distributed simulators using these algorithms. An "avalanche" phenomenon was observed in the deadlock detection and recovery simulator, and was found to be a necessary condition for achieving good performance. The central server queueing model was also examined. The poor behavior of this test case that has been observed by others is reproduced in the testbed, and explained in terms of message population and lookahead. Based on these observations, a modification to the server process program is suggested that improves performance by as much as an order of magnitude when firstcome- first-serve (FCFS) servers are used. These results demonstrate that conservative distributed simulation algorithms using deadlock avoidance or detection and recovery techniques can provide significant speedups over sequential event list implementations for some workloads, even in the presence of only a moderate amount of parallelism and many feedback loops. However, a moderate to high degree of parallelism is not sufficient to guarantee good performance

Implementing a time-driven simulation on a MJIMD computer using a SIMD language

It often makes sense to write a program in the SIMD style, even if the program is to execute on a MIMD computer. Simulating physical events, in which all motion takes place simultaneously, is one area in which SIMD languages fit the applications particularly well. In this paper we present the SIMD programming language Dataparallel C and describe how we compile Dataparallel C programs into C code suitable for efficient execution on shared memory multiprocessors. We outline the parallel implementation of the Wa-Tor model and benchmark the performance of the compiled Dataparallel C program on the Sequent Balance and Sequent Symmetry multiprocessors

Application of Parallel Processing for Object Oriented Discrete Event Simulation of Manufacturing Systems

Industrial Engineering and Managemen