Process-induced skew reduction in nominal zero-skew clock trees

Abstract — This work develops an analytic framework for clock tree analysis considering process variations that is shown to correspond well with Monte Carlo results. The analysis frame-work is used in a new algorithm that constructs deterministic nominal zero-skew clock trees that have reduced sensitivity to process variation. The new algorithm uses a sampling approach to perform route embedding during a bottom-up merging phase, but does not select the best embedding until the top-down phase. This results in clock trees that exhibit a mean skew reduction of 32.4 % on average and a standard deviation reduction of 40.7 % as verified by Monte Carlo. The average increase in total clock tree capacitance is less than 0.02%. I

Statistical clock skew analysis considering intra-die process variations

With shrinking cycle times, clock skew has become an increasingly difficult and important problem for high performance designs. Traditionally, clock skew has been analyzed using case-files which cannot model intra-die process variations and hence result in a very optimistic skew analysis. In this paper, we present a statistical skew analysis method to model intra-die process variations. We first present a formal model of the statistical clock skew problem and then propose an algorithm which is based on propagation of joint probability distribution functions in a bottom up fashion in a clock tree. The analysis accounts for topological correlations between path delays and has linear run time with the size of the clock tree. The proposed method was tested on several large clock tree circuits, including a clock tree from a large industrial high-performance microprocessor. The results are compared with Monte Carlo simulatio

A Dynamic Back End of the Line Customization Technique for Yield Improvement

Abstract A Dynamic Back End of the Line Customization Technique for Yield Improvement Ardavan Aryanpour, M. Sc July 2010 As CMOS technology evolves and transistors get smaller, although chip manufacturers benefit significantly from being able to fit more transistors in a smaller area and also producing chips with lower power dissipation, they have to confront newer problems that are directly related to the size of transistors and the thickness of the deposited layers on a wafer. Smaller transistors are faster and dissipate less power, but the smaller the technology becomes, the harder the fabrication process is to control. Thin silicon, metal and oxide layers must be accurately deposited because any variation in the thickness will cause unexpected behavior in the device. These variations affect many parameters in CMOS. Any slight change in temperature, doping density, deposition timing, etc., can cause a significant change of characteristics of a CMOS device and the variation caused by these changes is called Process Variation (PV). In this thesis, two circuits are taken into study in order to understand how process variation impacts the electrical specifications of a circuit example. The first example is a tapered buffer chain and the second example is a senseamplifier flip flop. The idea is to propose a technique to decrease the loss percentage (Increase the yield). Basically for one specific design a few variant circuit layouts with different power-speed specifications are implemented and based on the results of the mid fabrication measurements on the test circuits that are deposited throughout the wafer, one of them is chosen with the means of choosing a proper masking sequence. The electrical characteristics of the i

Non-invasive IC tomography using spatial correlations

We introduce a new methodology for post-silicon characterization of the gate-level variations in a manufactured Integrated Circuit (IC). The estimated characteristics are based on the power and the delay measurements that are affected by the process variations. The power (delay) variations are spatially correlated. Thus, there exists a basis in which variations are sparse. The sparse representation suggests using the L1-regularization (the compressive sensing theory). We show how to use the compressive sensing theory to improve post-silicon characterization. We also address the problem by adding spatial constraints directly to the traditional L2-minimization. The proposed methodology is fast, inexpensive, non-invasive, and applicable to legacy designs. Noninvasive IC characterization has a range of emerging applications, including post-silicon optimization, IC identification, and variations' modeling/simulations. The evaluation results on standard benchmark circuits show that, in average, the gate level characteristics estimation accuracy can be improved by more than two times using the proposed methods

Layout optimization in ultra deep submicron VLSI design

As fabrication technology keeps advancing, many deep submicron (DSM) effects have become increasingly evident and can no longer be ignored in Very Large Scale Integration (VLSI) design. In this dissertation, we study several deep submicron problems (eg. coupling capacitance, antenna effect and delay variation) and propose optimization techniques to mitigate these DSM effects in the place-and-route stage of VLSI physical design. The place-and-route stage of physical design can be further divided into several steps: (1) Placement, (2) Global routing, (3) Layer assignment, (4) Track assignment, and (5) Detailed routing. Among them, layer/track assignment assigns major trunks of wire segments to specific layers/tracks in order to guide the underlying detailed router. In this dissertation, we have proposed techniques to handle coupling capacitance at the layer/track assignment stage, antenna effect at the layer assignment, and delay variation at the ECO (Engineering Change Order) placement stage, respectively. More specifically, at layer assignment, we have proposed an improved probabilistic model to quickly estimate the amount of coupling capacitance for timing optimization. Antenna effects are also handled at layer assignment through a linear-time tree partitioning algorithm. At the track assignment stage, timing is further optimized using a graph based technique. In addition, we have proposed a novel gate splitting methodology to reduce delay variation in the ECO placement considering spatial correlations. Experimental results on benchmark circuits showed the effectiveness of our approaches