5 research outputs found
State Dependent Statistical Timing Model for Voltage Scaled Circuits
This paper presents a novel statistical state-dependent timing model for
voltage over scaled (VoS) logic circuits that accurately and rapidly finds the
timing distribution of output bits. Using this model erroneous VoS circuits can
be represented as error-free circuits combined with an error-injector. A case
study of a two point DFT unit employing the proposed model is presented and
compared to HSPICE circuit simulation. Results show an accurate match, with
significant speedup gains
Modeling and Energy Optimization of LDPC Decoder Circuits with Timing Violations
This paper proposes a "quasi-synchronous" design approach for signal
processing circuits, in which timing violations are permitted, but without the
need for a hardware compensation mechanism. The case of a low-density
parity-check (LDPC) decoder is studied, and a method for accurately modeling
the effect of timing violations at a high level of abstraction is presented.
The error-correction performance of code ensembles is then evaluated using
density evolution while taking into account the effect of timing faults.
Following this, several quasi-synchronous LDPC decoder circuits based on the
offset min-sum algorithm are optimized, providing a 23%-40% reduction in energy
consumption or energy-delay product, while achieving the same performance and
occupying the same area as conventional synchronous circuits.Comment: To appear in IEEE Transactions on Communication
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State dependent statistical timing model for voltage scaled circuits
This paper presents a novel statistical state-dependent timing model for voltage over scaled (VoS) logic circuits that accurately and rapidly finds the timing distribution of output bits. Using this model erroneous VoS circuits can be represented as error-free circuits combined with an error-injector. A case study of a two point DFT unit employing the proposed model is presented and compared to HSPICE circuit simulation. Results show an accurate match, with significant speedup gains. © 2014 IEEE