Carbonyl-Iron/Epoxy Composite Magnetic Core for Planar Power Inductor Used in Package-Level Power Grid

Our research objective is to realize the basic technology for a next generation package-level power grid (PLPG) for plural application large scale integrated circuits (LSIs). In this study, a carbonyl-iron powder (CIP)/epoxy composite magnetic core, for large-current power inductor used for the main dc-dc converter in the PLPG, has been fabricated and evaluated. 54 vol.%-CIP/epoxy composite core made by screen-printing had a relative permeability of 7.5 and loss tangent of about 0.03 at 100 MHz. The planar power inductor using composite core was fabricated and evaluated, which had a quasi closed magnetic circuit consisting of low permeability composite core and embedded 35-mu m-thick, two-turn copper spiral coil. The fabricated inductor with a 1-mm-square in size had 5.5 nH inductance, Q-factor of 15 at 100 MHz, and 18 m Omega dc coil resistance. Inductance was constant even when the superimposed dc current increased up to around 5.5 A.ArticleIEEE TRANSACTIONS ON MAGNETICS. 49(7):4172-4175 (2013)journal articl

Embedded Planar Power Inductor in an Organic Interposer for Package-Level DC Power Grid

To realize the basic technology of a package-level dc power grid for the next generation power delivery to large scale integrated circuits (LSIs), two types of planar spiral inductors embedded in an organic interposer, for several tens of megahertz switching power supply integrated in LSI package, have been proposed. One is a Zn-Fe ferrite core spiral inductor, and another is a hybrid core spiral inductor, with quasi closed magnetic circuit consisting of the bottom Zn-Fe ferrite core and top carbonyl-iron/epoxy composite core. In this paper, the two types of planar spiral inductors have been fabricated and evaluated. From the experimental results, it was found that the hybrid core planar spiral inductor exhibited higher Q-factor and larger rating dc current than the Zn-Fe ferrite core inductor.ArticleIEEE TRANSACTIONS ON MAGNETICS. 50(11):8401304 (2014)journal articl

Design Methologies for Integrated Inductor-Based Soft-Switching DC DC Converters

This paper presents a study on resonant converter topologies targeted for CMOS integration. Design methodologies to optimize efficiency for the integration of Quasi-Resonant and Quasi-Square-Wave converters are proposed. A power loss model is used to optimize the design parameters of the power stage, including the driver circuits, and also to conclude about CMOS technology limitations. Based on this discussion, and taking as reference a 0.35μm CMOS process, two converters are designed to validate the proposal: a Quasi Resonant boost converter operating at 100MHz and a Quasi-Square-Wave buck converter operating at 70MHz. Simulation results confirm the feasibility of these topologies for monolithic integration

Fabrication of Planar Power Inductor for Embedded Passives in LSI Package for Hundreds Megahertz Switching DC-DC Buck Converter

Recently, research and development of integrated low-voltage dc-dc converter to LSIs has been active. In order to realize such integrated dc power supply, power magnetic devices must be integrated in it. The authors have fabricated planar power inductor embedded in LSI package for hundreds megahertz switching dc-dc buck converter. In this study, two types of planar power inductors have been fabricated: one was spin-sprayed Zn-ferrite thick film magnetic core inductor, and the other was composite magnetic core (Fe-based amorphous/polyimide) inductor. Footprint of the fabricated inductors was 850 x 850 mu m(2), their inductance was about 10 nH, and the quality factor Q was about 20 at 100 MHz. The rating current which depends on the superimposed dc characteristic was at least up to 2 A.ArticleIEEE TRANSACTIONS ON MAGNETICS. 47(10):3204-3207 (2011)journal articl

An Overview of Fully Integrated Switching Power Converters Based on Switched-Capacitor versus Inductive Approach and Their Advanced Control Aspects

This paper reviews and discusses the state of the art of integrated switched-capacitor and integrated inductive power converters and provides a perspective on progress towards the realization of efficient and fully integrated DC–DC power conversion. A comparative assessment has been presented to review the salient features in the utilization of transistor technology between the switched-capacitor and switched inductor converter-based approaches. First, applications that drive the need for integrated switching power converters are introduced, and further implementation issues to be addressed also are discussed. Second, different control and modulation strategies applied to integrated switched-capacitor (voltage conversion ratio control, duty cycle control, switching frequency modulation, Ron modulation, and series low drop out) and inductive converters (pulse width modulation and pulse frequency modulation) are then discussed. Finally, a complete set of integrated power converters are related in terms of their conditions and operation metrics, thereby allowing a categorization to provide the suitability of converter technologies

Dual-frequency single-inductor multiple-output (DF-SIMO) power converter topology for SoC applications

Modern mixed-signal SoCs integrate a large number of sub-systems in a single nanometer CMOS chip. Each sub-system typically requires its own independent and well-isolated power supply. However, to build these power supplies requires many large off-chip passive components, and thus the bill of material, the package pin count, and the printed circuit board area and complexity increase dramatically, leading to higher overall cost. Conventional (single-frequency) Single-Inductor Multiple-Output (SIMO) power converter topology can be employed to reduce the burden of off-chip inductors while producing a large number of outputs. However, this strategy requires even larger off-chip output capacitors than single-output converters due to time multiplexing between the multiple outputs, and thus many of them suffer from cross coupling issues that limit the isolation between the outputs. In this thesis, a Dual-Frequency SIMO (DF-SIMO) buck converter topology is proposed. Unlike conventional SIMO topologies, the DF-SIMO decouples the rate of power conversion at the input stage from the rate of power distribution at the output stage. Switching the input stage at low frequency (~2 MHz) simplifies its design in nanometer CMOS, especially with input voltages higher than 1.2 V, while switching the output stage at higher frequency enables faster output dynamic response, better cross-regulation, and smaller output capacitors without the efficiency and design complexity penalty of switching both the input and output stages at high frequency. Moreover, for output switching frequency higher than 100 MHz, the output capacitors can be small enough to be integrated on-chip. A 5-output 2-MHz/120-MHz design in 45-nm CMOS with 1.8-V input targeting low-power microcontrollers is presented as an application. The outputs vary from 0.6 to 1.6 V, with 4 outputs providing up to 15 mA and one output providing up to 50 mA. The design uses single 10-uH off-chip inductor, 2-nF on-chip capacitor for each 15-mA output and 4.5-nF for the 50-mA output. The peak efficiency is 73%, Dynamic Voltage Scaling (DVS) is 0.6 V/80 ns, and settling time is 30 ns for half-to-full load steps with no observable overshoot/undershoot or cross-coupling transients. The DF-SIMO topology enables realizing multiple efficient power supplies with faster dynamic response, better cross-regulation, and lower overall cost compared to conventional SIMO topologies

Implementation of an Integrated LC Component for the Output Filter of a Step-Down DC-DC Converter

The implementation of a fabricated integrated LC component for output filter of a low-power step-down DC-DC converter is presented in this paper. The topology of the LC filter has both inductor and capacitor stacked together in planar structure to form an integrated hybrid LC component. Flexible ferrite sheets are used for inductor magnetic core and capacitor dielectric substrate since ferrite materials combine both magnetic and dielectric properties. The use of these types of ferrite allows new filter topology to be investigated and also simplifies manufacturing process. The active part and the passive integrated LC output filter achieve a maximum power efficiency of 68% for output power of 1.2 W. Experimental results of the functioning of the converter are presented and discussed

Integrated Microfluidic Power Generation and Cooling for Bright Silicon MPSoCs

The soaring demand for computing power in our digital information age has produced as collateral undesirable effect a surge in power consumption and heat density for computing servers. Accordingly, 30-40% of the energy consumed in state-of-the-art servers is dissipated in cooling. The remaining energy is used for computation, and causes the temperature ramp-up to operating conditions that already preclude operating all the cores at maximum performance levels, in order to prevent system overheating and failures. This situation is set to worsen as shipments of high-end (i.e., even denser) many-core servers are increasing at a 25% compound annual growth rate. Thus, state-of-the-art worst-case power and cooling delivery solutions on servers are reaching their limits and it will no longer be possible to power up simultaneously all the available on-chip cores (situation known as the existence of "dark silicon"); hence, drastically limiting the benefits of technology scaling. This presentation aims to completely revise the prevailing worst-case power and cooling provisioning paradigm for servers by championing a disruptive approach to computing server architecture design that prevents dark silicon. This proposed approach integrates a flexible heterogeneous many-core architecture template with an on-chip microfluidic fuel cell network for joint cooling delivery and power supply (i.e., local power generation and delivery), as well as a holistic power-temperature model predictive controller exploiting the server software stack, in order to achieve scalable and energy-minimal server architectures. Thanks to the disruptive system-level many-core architecture with microfluidic power and cooling delivery, as well as the complementary temperature control, we can envision the removal of the current limits of power delivery and heat dissipation in server designs, subsequently avoiding dark silicon in future servers and enabling new perspectives in future energy-proportional server designs

Reducing Power Loss, Cost and Complexity of SoC Power Delivery Using Integrated 3-Level Voltage Regulators

Traditional methods of system-on-chip (SoC) power management based on dynamic voltage and frequency scaling (DVFS) is limited by 1) cores/IP blocks sharing a voltage domain provided by off-chip voltage regulators (VR) and 2) slow voltage scaling time $(<0.1V/\mu s)$. This global, slow DVFS cannot track the increasingly heterogeneous, fluctuating performance requirements of individual microprocessor cores and SoC components. Furthermore, traditional off-chip VRs add significant area overhead and component cost on the board. This thesis explores replacing a large portion of existing off-chip VRs with integrated voltage regulators (IVR) that can scale the voltage at a 50 mV/ns rate, which is 500 times faster than microsecond-scale voltage scaling with existing off-chip VRs. IVRs occupy 10 times smaller footprint than off-chip VRs, making it easy to duplicate them to provide per-core or per-IP-block voltage control. This thesis starts by summarizing the benefits of using IVRs to deliver power to SoCs. Based on a simulation study targeting a 1.6W, 4-core SoC, I show that greater than 20% energy savings is possible with fast, per-core DVFS enabled by IVRs. Next, I present two stand-alone IVR test-chips converting 1.8V and 2.4V to 0.4-1.4V while delivering maximum 1W to the output. Both test-chips incorporate a 3-level VR topology, which is suitable for integration because the topology allows for much smaller inductors (1nH) than existing inductor-based buck VRs. I also discuss reasons behind lower-than-simulated efficiencies in the test-chips and ways to improve. Finally, I conclude with future process technologies that can boost IVR conversion efficiencies and power densities.Engineering and Applied Science