Reduced-Rank STAP Schemes for Airborne Radar Based on Switched Joint Interpolation, Decimation and Filtering Algorithm

In this paper, we propose a reduced-rank space-time adaptive processing (STAP) technique for airborne phased array radar applications. The proposed STAP method performs dimensionality reduction by using a reduced-rank switched joint interpolation, decimation and filtering algorithm (RR-SJIDF). In this scheme, a multiple-processing-branch (MPB) framework, which contains a set of jointly optimized interpolation, decimation and filtering units, is proposed to adaptively process the observations and suppress jammers and clutter. The output is switched to the branch with the best performance according to the minimum variance criterion. In order to design the decimation unit, we present an optimal decimation scheme and a low-complexity decimation scheme. We also develop two adaptive implementations for the proposed scheme, one based on a recursive least squares (RLS) algorithm and the other on a constrained conjugate gradient (CCG) algorithm. The proposed adaptive algorithms are tested with simulated radar data. The simulation results show that the proposed RR-SJIDF STAP schemes with both the RLS and the CCG algorithms converge at a very fast speed and provide a considerable SINR improvement over the state-of-the-art reduced-rank schemes

Algorithmic patterns for H\mathcal{H}-matrices on many-core processors

In this work, we consider the reformulation of hierarchical ($\mathcal{H}$) matrix algorithms for many-core processors with a model implementation on graphics processing units (GPUs). $\mathcal{H}$ matrices approximate specific dense matrices, e.g., from discretized integral equations or kernel ridge regression, leading to log-linear time complexity in dense matrix-vector products. The parallelization of $\mathcal{H}$ matrix operations on many-core processors is difficult due to the complex nature of the underlying algorithms. While previous algorithmic advances for many-core hardware focused on accelerating existing $\mathcal{H}$ matrix CPU implementations by many-core processors, we here aim at totally relying on that processor type. As main contribution, we introduce the necessary parallel algorithmic patterns allowing to map the full $\mathcal{H}$ matrix construction and the fast matrix-vector product to many-core hardware. Here, crucial ingredients are space filling curves, parallel tree traversal and batching of linear algebra operations. The resulting model GPU implementation hmglib is the, to the best of the authors knowledge, first entirely GPU-based Open Source $\mathcal{H}$ matrix library of this kind. We conclude this work by an in-depth performance analysis and a comparative performance study against a standard $\mathcal{H}$ matrix library, highlighting profound speedups of our many-core parallel approach