5,553 research outputs found
Wadge Degrees of -Languages of Petri Nets
We prove that -languages of (non-deterministic) Petri nets and
-languages of (non-deterministic) Turing machines have the same
topological complexity: the Borel and Wadge hierarchies of the class of
-languages of (non-deterministic) Petri nets are equal to the Borel and
Wadge hierarchies of the class of -languages of (non-deterministic)
Turing machines which also form the class of effective analytic sets. In
particular, for each non-null recursive ordinal there exist some -complete and some -complete -languages of Petri nets, and the supremum of
the set of Borel ranks of -languages of Petri nets is the ordinal
, which is strictly greater than the first non-recursive ordinal
. We also prove that there are some -complete, hence non-Borel, -languages of Petri nets, and
that it is consistent with ZFC that there exist some -languages of
Petri nets which are neither Borel nor -complete. This
answers the question of the topological complexity of -languages of
(non-deterministic) Petri nets which was left open in [DFR14,FS14].Comment: arXiv admin note: text overlap with arXiv:0712.1359, arXiv:0804.326
Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation
Detailed modeling of processors and high performance cycle-accurate
simulators are essential for today's hardware and software design. These
problems are challenging enough by themselves and have seen many previous
research efforts. Addressing both simultaneously is even more challenging, with
many existing approaches focusing on one over another. In this paper, we
propose the Reduced Colored Petri Net (RCPN) model that has two advantages:
first, it offers a very simple and intuitive way of modeling pipelined
processors; second, it can generate high performance cycle-accurate simulators.
RCPN benefits from all the useful features of Colored Petri Nets without
suffering from their exponential growth in complexity. RCPN processor models
are very intuitive since they are a mirror image of the processor pipeline
block diagram. Furthermore, in our experiments on the generated cycle-accurate
simulators for XScale and StrongArm processor models, we achieved an order of
magnitude (~15 times) speedup over the popular SimpleScalar ARM simulator.Comment: Submitted on behalf of EDAA (http://www.edaa.com/
A technique for detecting wait-notify deadlocks in Java
Deadlock analysis of object-oriented programs that dynamically create threads and objects is complex, because these programs may have an infinite number of states.
In this thesis, I analyze the correctness of wait - notify patterns (e.g. deadlock freedom) by using a newly introduced technique that consists in an analysis model that is a basic concurrent language with a formal semantic. I detect deadlocks by associating a Petri Net graph to each process of the input program. This model allows to check if a deadlock occur by analysing the reachability tree.
The technique presented is a basic step of a more complex and complete project, since in my work I only consider programs with one object
Design of testbed and emulation tools
The research summarized was concerned with the design of testbed and emulation tools suitable to assist in projecting, with reasonable accuracy, the expected performance of highly concurrent computing systems on large, complete applications. Such testbed and emulation tools are intended for the eventual use of those exploring new concurrent system architectures and organizations, either as users or as designers of such systems. While a range of alternatives was considered, a software based set of hierarchical tools was chosen to provide maximum flexibility, to ease in moving to new computers as technology improves and to take advantage of the inherent reliability and availability of commercially available computing systems
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The P3 platform: an approach and software system for developing diagrammatic model-based methods in design research
Many issues in design and design management have been explored by building models which capture the relationships between different aspects of the problem at hand. These models require computer support to construct and analyse. However, appropriate modelling tools can be time-consuming to develop in a research environment. Reflecting upon five design research projects, this paper proposes that such projects can be facilitated by recognising the iterative and tightly-coupled nature of research and tool development, and by attempting to minimise the effort of solution prototyping within this process. Our approach is enabled by a software platform which can be rapidly configured to implement many conceivable modelling approaches. This configurability is complemented by an emerging library of modelling and analysis approaches tailored to explore design process systems. The platform-based approach enables any mix of modelling concepts to be easily created. We propose it could thus help researchers to explore a wide range of questions without being constrained to existing conventions for modelling – or for model integration
Semantic Embedding of Petri Nets into Event-B
We present an embedding of Petri nets into B abstract systems. The embedding
is achieved by translating both the static structure (modelling aspect) and the
evolution semantics of Petri nets. The static structure of a Petri-net is
captured within a B abstract system through a graph structure. This abstract
system is then included in another abstract system which captures the evolution
semantics of Petri-nets. The evolution semantics results in some B events
depending on the chosen policies: basic nets or high level Petri nets. The
current embedding enables one to use conjointly Petri nets and Event-B in the
same system development, but at different steps and for various analysis.Comment: 16 pages, 3 figure
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