Architecture and Algorithm for a Stochastic Soft-output MIMO Detector

In this paper, we propose a novel architecture for a soft-output stochastic detector in multiple-input, multiple-output (MIMO) systems. The stochastic properties of this detector are studied and derived in this work, and several complexity reduction techniques are proposed to significantly reduce its cost from an architecture-implementation perspective. We also propose an efficient architecture to implement this detector. Finally, this detector is incorporated into an iterative detectiondecoding structure, and through simulations, it is shown that the overall frame error rate (FER) performance and complexity is of the same order as that of the conventional K-best sphere detector.Nokia CorporationXilinx Inc.National Science Foundatio

Reconfigurable Real-time MIMO Detector on GPU

In a high performance multiple-input multiple-output (MIMO) system, a soft output MIMO detector combined with a channel decoder is often used at the receiver to maximize performance gain. Graphic processor unit (GPU) is a low-cost parallel programmable co-processor that can deliver extremely high computation throughput and is well suited for signal processing applications. We propose and implement a novel soft MIMO detection algorithm and show we meet real-time performance while maintaining flexibility using GPU.NokiaNokia Siemens Networks (NSN)Texas InstrumentsXilinxNational Science Foundatio

High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm

In this paper, we propose a novel path-preserving trellis-search (PPTS) algorithm and its high-speed VLSI architecture for soft-output multiple-input-multiple-output (MIMO) detection. We represent the search space of the MIMO signal with an unconstrained trellis, where each node in stage of the trellis maps to a possible complex-valued symbol transmitted by antenna. Based on the trellis model, we convert the soft-output MIMO detection problem into a multiple shortest paths problem subject to the constraint that every trellis node must be covered in this set of paths. The PPTS detector is guaranteed to have soft information for every possible symbol transmitted on every antenna so that the log-likelihood ratio (LLR) for each transmitted data bit can be more accurately formed. Simulation results show that the PPTS algorithm can achieve near-optimal error performance with a low search complexity. The PPTS algorithm is a hardware-friendly data-parallel algorithm because the search operations are evenly distributed among multiple trellis nodes for parallel processing. As a case study, we have designed and synthesized a fully-parallel systolic-array detector and two folded detectors for a 4x4 16-QAM system using a 1.08 V TSMC 65-nm CMOS technology.With a 1.18 mm2 core area, the folded detector can achieve a throughput of 2.1 Gbps.With a 3.19 mm2 core area, the fully-parallel systolic-array detector can achieve a throughput of 6.4 Gbps

Low complexity scalable MIMO sphere detection through antenna detection reordering

This paper describes a novel low complexity scalable multiple-input multiple-output (MIMO) detector that does not require preprocessing and the optimal squared l2-norm computations to achieve good bit error (BER) performance. Unlike existing detectors such as Flexsphere that use preprocessing before MIMO detection to improve performance, the proposed detector instead performs multiple search passes, where each search pass detects the transmit stream with a different permuted detection order. In addition, to reduce the number of multipliers required in the design, we use l1-norm in place of the optimal squared l2-norm. To ameliorate the BER performance loss due to l1- norm, we propose squaring then scaling the l1-norm. By changing the number of parallel search passes and using norm scaling, we show that this design achieves comparable performance to Flexsphere with reduced resource requirement or achieves BER performance close to exhaustive search with increased resource requirement.National Science Foundatio

High-Performance Turbo-MIMO System Design with Iterative Soft-Detection and Decoding

Abstract-In turbo-multiple-input multiple-output (Turbo-MIMO) systems, the soft-output MIMO detector can provide the priori information to the turbo decoder. Unfortunately, if Rayleigh fading channels are applied, the induced unreliable priori information would cause the system performance degradation. In this paper, we proposed an iterative method to acquire the high reliability priori information from MIMO softdetector in Turbo-MIMO systems. Similar to the conventional updating rules in the turbo decoding algorithm, we utilize the extrinsic information from the turbo decoder to update the loglikelihood ratios (LLRs) based on log-MAP algorithm in the list sphere decoding (LSD) algorithm. To reduce the overall computational complexity, different iteration profiles are also discussed. Simulation results show that the proposed Turbo-MIMO system can significantly improve the system performance compared to that of the conventional Turbo-MIMO system

A Novel VLSI Architecture of Fixed-complexity Sphere Decoder

Fixed-complexity Sphere Decoder (FSD) is a recently proposed technique for Multiple-Input Multiple-Output (MIMO) detection. It has several outstanding features such as constant throughput and large potential parallelism, which makes it suitable for efficient VLSI implementation. However, to our best knowledge, no VLSI implementation of FSD has been reported in the literature, although some FPGA prototypes of FSD with pipeline architecture have been developed. These solutions achieve very high throughput but at very high cost of hardware resources, making them impractical in real applications. In this paper, we present a novel four-nodes-per-cycle parallel architecture of FSD, with a breadth-first processing that allows for short critical path. The implementation achieves a throughput of 213.3 Mbps at 400 MHz clock frequency, at a cost of 0.18 mm2 Silicon area on 0.13{\mu}m CMOS technology. The proposed solution is much more economical compared with the existing FPGA implementations, and very suitable for practicl applications because of its balanced performance and hardware-complexity; moreover it has the flexibility to be expanded into an eight-nodes-per-cycle version in order to double the throughput.Comment: 8 pages, this paper has been accepted by the conference DSD 201

Improving MIMO Sphere Detection Through Antenna Detection Order Scheduling

This paper proposes a novel scalable Multiple-Input Multiple-Output (MIMO) detector that does not require preprocessing to achieve good bit error rate (BER) performance. MIMO processing is a key technology in broadband wireless technologies such as 3G LTE, WiMAX, and 802.11n. Existing detectors such as Flexsphere use preprocessing before MIMO detection to improve performance. Instead of costly preprocessing, the proposed detector schedules multiple search passes, where each search pass detects the transmit stream with a different permuted detection order. By changing the number of parallel search passes, we show that this scalable detector can achieve comparable performance to Flexsphere with reduced resource requirement, or can eliminate LLR clipping and achieve BER performance within 0.25 dB of exhaustive search with increased resource requirement