Intermittent Excitation of High-Q Resonators for Low-Power High-Speed Clock Generation

There is growing demand for circuits that can provide ever greater performance from a minimal power budget. Example applications include wireless sensor nodes, mobile devices, and biomedical implants. High speed clock circuits are an integral part of such systems, playing roles such as providing digital processor clocks, or generating wireless carrier signals; this clock generation can often take a large part of a system’s power budget. Common techniques to reduce power consumption generally involve reducing the clock speed, and/or complex designs using a large circuit area. This paper proposes an alternative method of clock generation based on driving a high-Q resonator with a periodic chain of impulses. In this way, power consumption is reduced when compared to traditional resonator based designs; this power reduction comes at the cost of increased period jitter. A circuit was designed and laid out in 0.18µm CMOS, and was simulated in order to test the technique. Simulation results suggest that the circuit can achieve a FoM of 4.89GHz/mW, with a peak period jitter of 10.2ps at 2.015GHz, using a model resonator with a Q-factor of 126

A 4-channel 12-bit high-voltage radiation-hardened digital-to-analog converter for low orbit satellite applications

This paper presents a circuit design and an implementation of a four-channel 12-bit digital-to-analog converter (DAC) with high-voltage operation and radiation-tolerant attribute using a specific CSMC H8312 0.5-μm Bi-CMOS technology to achieve the functionality across a wide-temperature range from -55 °C to 125 °C. In this paper, an R-2R resistor network is adopted in the DAC to provide necessary resistors matching which improves the DAC precision and linearity with both the global common centroid and local common centroid layout. Therefore, no additional, complicated digital calibration or laser-trimming are needed in this design. The experimental and measurement results show that the maximum frequency of the single-chip four-channel 12-bit R-2R ladder high-voltage radiation-tolerant DAC is 100 kHz, and the designed DAC achieves the maximum value of differential non-linearity of 0.18 LSB, and the maximum value of integral non-linearity of -0.53 LSB at 125 °C, which is close to the optimal DAC performance. The performance of the proposed DAC keeps constant over the whole temperature range from -55 °C to 125 °C. Furthermore, an enhanced radiation-hardened design has been demonstrated by utilizing a radiation chamber experimental setup. The fabricated radiation-tolerant DAC chipset occupies a die area of 7 mm x 7 mm in total including pads (core active area of 4 mm x 5 mm excluding pads) and consumes less than 525 mW, output voltage ranges from -10 to +10 V

A 64mW DNN-based Visual Navigation Engine for Autonomous Nano-Drones

Fully-autonomous miniaturized robots (e.g., drones), with artificial intelligence (AI) based visual navigation capabilities are extremely challenging drivers of Internet-of-Things edge intelligence capabilities. Visual navigation based on AI approaches, such as deep neural networks (DNNs) are becoming pervasive for standard-size drones, but are considered out of reach for nanodrones with size of a few cm${}^\mathrm{2}$. In this work, we present the first (to the best of our knowledge) demonstration of a navigation engine for autonomous nano-drones capable of closed-loop end-to-end DNN-based visual navigation. To achieve this goal we developed a complete methodology for parallel execution of complex DNNs directly on-bard of resource-constrained milliwatt-scale nodes. Our system is based on GAP8, a novel parallel ultra-low-power computing platform, and a 27 g commercial, open-source CrazyFlie 2.0 nano-quadrotor. As part of our general methodology we discuss the software mapping techniques that enable the state-of-the-art deep convolutional neural network presented in [1] to be fully executed on-board within a strict 6 fps real-time constraint with no compromise in terms of flight results, while all processing is done with only 64 mW on average. Our navigation engine is flexible and can be used to span a wide performance range: at its peak performance corner it achieves 18 fps while still consuming on average just 3.5% of the power envelope of the deployed nano-aircraft.Comment: 15 pages, 13 figures, 5 tables, 2 listings, accepted for publication in the IEEE Internet of Things Journal (IEEE IOTJ

Smart Energy-Efficient Clock Synthesizer for Duty-Cycled Sensor SoCs in 65 nm/28nm CMOS

Duty-cycled low-rate Internet-of-things (IoT) sensors are employed in diverse applications, requiring configurable and energy-efficient on-chip and on-demand clock synthesis. We present an all-digital frequency-locked loop (AD-FLL) capable of generating an accurate clock selectively in stand-alone operation or locked to a 32kHz reference. We report measurement results of two prototypes in 65nm and 28nm CMOS offering a configurable clock multiplication factor of up to 32 786, resulting in a wide tuning-range from a few MHz to 2.4GHz and 1.6GHz, respectively. The challenges of slow start-up and deterministic jitter are addressed by a fast hybrid-mode start-up procedure and by various jitter reduction modes. We also introduce the concept of Transient Clocking that leverages the capabilities of the proposed AD-FLL to make a system operational after cold-start or wake-up before the supply voltage has stabilized. We study two application examples that highlight the versatility of the concept in IoT applications and show its potential to amortize the time and energy cost of typical system start-up tasks, like state-restoration or wake-up event classification