Phase-transition induced optimization on electrostrain, electrocaloric refrigeration and energy storage of LiNbO3 doped BNT-BT ceramics

((Bi0.5Na0.5TiO3)0.88-(BaTiO3)0.12)(1-x)-(LiNbO3)x (x = 0.0, 0.01, 0.02, 0.03, 0.04, 0.05, 0.06, and 0.07; abbreviated as LiNbO3-doped BNT-BT) ceramics possessing many excellent performances (large electrostrain, negative electrocaloric effect and energy storage density with high efficiency) was fabricated by the conventional solid-state reaction method. A large electrostrain (maximum ~ 0.34% at 100 kV/cm and room temperature) with high thermal stability over a broad temperature range (~80 K) is obtained at x = 0.03. A large energy storage density (maximum Wenergy ~ 0.665 J/cm3 at 100 kV/cm and room temperature) with a high efficiency (η ~ 49.3%) is achieved at x = 0.06. Moreover, a large negative electrocaloric (EC) effect (maximum ΔT ~ 1.71 K with ΔS ~ - 0.22 J/(K kg) at 70 kV/cm)) is also obtained at x = 0.04. Phase transition (from ferroelectric to antiferroelectric and then to relaxor) induced by increasing the doping amount of LiNbO3 plays a very key role on the optimization of these performances. These findings and breakthroughs make the LiNbO3-doped BNT-BT ceramics very promising candidates as multifunctional materials

Reliability study of Zr and Al incorporated hf based high-k dielectric deposited by advanced processing

Hafnium-based high-x dielectric materials have been successfully used in the industry as a key replacement for SiO2 based gate dielectrics in order to continue CMOS device scaling to the 22-nm technology node. Further scaling according to the device roadmap requires the development of oxides with higher x values in order to scale the equivalent oxide thickness (EOT) to 0.7 nm or below while achieving low defect densities. In addition, next generation devices need to meet challenges like improved channel mobility, reduced gate leakage current, good control on threshold voltage, lower interface state density, and good reliability. In order to overcome these challenges, improvements of the high-x film properties and deposition methods are highly desirable. In this dissertation, a detail study of Zr and Al incorporated HfO2 based high-κ dielectrics is conducted to investigate improvement in electrical characteristics and reliability. To meet scaling requirements of the gate dielectric to sub 0.7 nm, Zr is added to HfO2 to form Hf1-xZrxO2 with x=0, 0.31 and 0.8 where the dielectric film is deposited by using various intermediate processing conditions, like (i) DADA: intermediate thermal annealing in a cyclical deposition process; (ii) DSDS: similar cyclical process with exposure to SPA Ar plasma; and (iii) As-Dep: the dielectric deposited without any intermediate step. MOSCAPs are formed with TiN metal gate and the reliability of these devices is investigated by subjecting them to a constant voltage stress in the gate injection mode. Stress induced flat-band voltage shift (ΔVFB), stress induced leakage current (SILC) and stress induced interface state degradation are observed. DSDS samples demonstrate the superior characteristics whereas the worst degradation is observed for DADA samples. Time dependent dielectric breakdown (TDDB) shows that DSDS Hf1-xZrxO2 (x=0.8) has the superior characteristics with reduced oxygen vacancy, which is affiliated to electron affinity variation in HfO2 and ZrO2. The trap activation energy levels estimated from the temperature dependent current voltage characteristics also support the observed reliability characteristics for these devices. In another experiment, HfO2 is lightly doped with Al with a variation in Al concentration by depositing intermediate HfAlOx layers. This work has demonstrated a high quality HfO2 based gate stack by depositing atomic layer deposited (ALD) HfAlOx along with HfO2 in a layered structure. In order to get multifold enhancement of the gate stack quality, both Al percentage and the distribution of Al are observed by varying the HfAlOx layer thickness and it is found that \u3c 2% Al/(Al+Hf)% incorporation can result in up to 18% reduction in the average EOT along with up to 41 % reduction in the gate leakage current as compared to the dielectric with no Al content. On the other hand, excess Al presence in the interfacial layer moderately increases the interface state density (Dit). When devices are stressed in the gate injection mode at a constant voltage stress, dielectrics with Al/(Hf+Al)% \u3c 2% show resistance to stress induced flat-band voltage shift (ΔVFB), and stress induced leakage current (SILC). The time dependent dielectric breakdown (TDDB) characteristics show a higher charge to breakdown and an increase in the extracted Weibull slope (β) that further confirms an enhanced dielectric reliability for devices with \u3c 2% Al/(Al+Hf)%

Electrical characterisation of emerging photo anodes suited to water dissociation with an applied bias

One of the pivotal challenges of the 21st century is to develop alternative energy sources to replace the inevitable depletion of fossil fuels. One candidate for a non-polluting, abundant and renewable source of energy is sunlight. The significant challenge for the large-scale uptake of solar energy is overcoming the intermittent nature of solar radiation using energy storage methods. Synthesis of fuels from sunlight is one potential storage approach, providing the need for optimized photo-electrochemical devices and materials. The direct photovoltage of water to produce hydrogen and oxygen represents the most direct route to the synthesis of clean fuel. Recently it has been showing that technology from the microelectronics industry can be used to fabricate metal oxide semiconductors for use as photoanodes. Given that the protective oxide needs to be transparent to allow light to the photoactive material, two possible solutions are available. To have a thicker transparent conducting oxide, such as indium-tin-oxide, which would create a Schottky junction with the silicon below, or to use very thin oxides such as titanium dioxide, which when a catalyst is deposited on top creates a MOS structure. Of interest to the first option are the electrical properties of the Schottky junction in particular the barrier height, as this will dictate the current flow through to the water and drive the electrochemical reaction. For the second option to be successful, the thin oxide must not have any pinholes, i.e. to isolate the photoactive material below from the water. Atomic layer deposition is able to provide this level of conformality. A conduction mechanism study was performed and an investigation into the relationship between the stoichiometry of the titanium dioxide and the leakage current. It was shown that the level of oxygen vacancies played a key role in the level of leakage current, but a dominant conduction mechanism was not proved. Next a study into how the thickness affects the conduction through the films was performed, where results show that an increased thickness results in an increased leakage current, opposite of what would be expected. Some ellipsometry data shows a definite change in the films as they get thicker. The relationship between these electrical properties and the electrochemical properties of interested in a water splitting cell were also studied and shown that it is not always possible to compare the two, especially when, the electrochemical measurement includes a light source. In addition, an investigation into deposition of mixed oxides based on titanium dioxide, was undertaken, using a novel ALD method whereby the titanium precursor was not pulsed in saturation. In this way a number of reaction sites were left unfilled, meaning that when a second metal precursor was pulsed, a single cycle of growth contained two different types of metal atoms, as opposed to the more traditional method of the supercycle detailed in chapter 1. The electrical properties of these films were measured, and a definitive trend showed that, creating mixed oxides in this way can change the electrical properties but that the incorporated amount of the second metal is an important factor. An anneal study was found to vastly change the electrical properties of these mixed oxides samples, where the leakage current fell by a number of orders of magnitude. For a water splitting application, this is not a desirable effect

Effect of Post Plasma Oxidation on Ge Gate Stacks Interface Formation

This work investigates the application of slot plane antenna plasma oxidation (SPAO) during dielectric deposition to process TiN/ZrO2/Al2O3/Ge MOS capacitors. The impact of SPAO exposure on effective oxide thickness (EOT), leakage current, interface state density (Dit), C-V hysteresis, oxide breakdown characteristics was studied. Considerable degradation of electrical properties was observed with SPAO being performed before Al2O3/ZrO2 gate stack deposition. When SPAO was performed in between Al2O3/ZrO2 deposition, moderate increase in EOT and significant decrease in Dit was observed. This can be attributed to the formation of a thicker GeOX layer. On the other hand, when SPAO was performed after the deposition of both the high-k layers, higher Dit was observed suggesting a GeO2 layer formation. Time zero dielectric breakdown (TZDB) characteristics indicate that plasma exposure after and in between Al2O3/ZrO2 deposition enhances the dielectric quality by film densification due to plasma exposure. It was also demonstrated that improved dielectric and interface quality can be achieved when ALD-Al2O3/ZrO2 gate stacks were exposed to SPAO

Interface states reduction in atomic layer deposited TiN/ZrO2/Al2O3/Ge gate stacks

In this work, the authors report the application and influence of slot plane antenna plasma oxidation (SPAO) on the quality of Ge/high-k based metal-oxide-semiconductor capacitors. The effect of SPAO exposure on the Ge/high-k interface during atomic layer deposition of the dielectric along with the reliability characteristics has been studied. A significant improvement in the electrical properties has been observed when the high-k stacks are exposed to SPAO treatment. The devices treated with SPAO after Al2O3/ZrO2 deposition (CASE-1) show slightly better equivalent oxide thickness, low leakage current density, and marginally better breakdown characteristics compared to the devices treated with SPAO in-between Al2O3/ZrO2 deposition (CASE-2). This can be attributed to the densification of the gate stack as the plasma exposed to the total stack and the formation of the thick interfacial layer as evident from the X-ray photoelectron spectroscopy (XPS) measurements. A stable and thin interfacial layer formation was observed from XPS data in the samples treated with SPAO in-between high-k stack deposition compared to the samples treated with SPAO after high-k stack deposition. This leads to the low interface state density, low hysteresis, comparable dielectric breakdown, and reliable characteristics in CASE-2 compared to CASE-1. On the other hand, XPS data revealed that the interface is deteriorated in the samples treated with SPAO before high-k stack deposition (CASE-3) and leads to poor electrical properties. Published by the AVS

Reliability Deterioration of Nitrided Gate Oxide Thin Films

在深次微米製程中，因短通道效應日益嚴重，多已將埋入通道PMOS之多晶矽閘極改為表面通道P+多晶矽閘極。表面通道的好處是載子經基材表面傳導，容易受閘極電壓的控制，因此表面通道要比埋入通道好控制許多。但PMOS閘極多晶矽需使用硼作為摻雜物，易產生硼會穿過氧化層/矽介面，進入基材而產生臨界電壓偏移現象。 目前製程上對於此問題所使用之解決方式，其中一個就是在形成閘極氧化層後採用氮化製程，來抑制P+ Poly內的摻雜硼原子對閘極氧化層的穿透與擴散至基底。然而使用傳統高温氮化法,因受限氮化濃度無法提升,以及先進製程對熱預算(thermal budget)的控制，早已無法滿足次世代製程技術要求。但電漿氮化製程卻擁有低溫，高氮化濃度以及高生產力等優點，使其成為次微米製程的主流。縱使有以上這些優點，氮濃度依然不能無限增加，因氮原子仍有機會擴散到SiO2/Si介面，導致元件特性退化以及衍生的元件可靠度壽命問題。 本論文由氧化層氮濃度分割實驗可得知，提高氮濃度有助於抑制P+閘極多晶矽內的摻雜硼原子穿透至基材且使等效氧化層厚度減少。但是當氮濃度由12.2%改變至14.3%時，閘極電流密度卻會大幅增加約30%且TDDB與NBTI壽命也會衰退約70-90%。此外，由TDDB測試結果指出PMOS壽命比NMOS短，直到當氮濃度到達14.3%時，二者壽命才會較為相近。而這表示NMOS單純只受到氮濃度影響，而PMOS則受到氮原子濃度及硼穿透效應雙重影響。藉由本實驗之結論，可得知氮濃度與可靠度壽命之關係，進而估算在產品10年保固的要求下，SPA(Slot plane Antenna)電漿氮化技術之氧化層氮化濃度之極限。For deep submicron meter process，short channel effect becomes worse and so PMOS device has been changed to surface channel from buried channel by P+ gate poly use. However，P+ gate poly needs to dope by Boron, but device threshold voltage happen shift issue due to Boron penetrate through Si/SiO2 to substrate easily .On the other hand，if devices reduce Boron dosage to prevent penetration problem，P+ poly may impact depletion issue and then induce performance deterioration. About solution of advanced process for this issue，nitrided gate oxide usually be used to block boron penetration. However，traditional thermal nitridation processes are limited to low nitrogen concentration in oxide and advanced processes restrict thermal budget. Plasma nitridation technologies haven’t above shortage，it provide low process temperature、high nitrogen concentration and high throughput…etc. But Nitrogen is unable to increase infinitely because nitrogen may diffuse to Si/SiO2 interface and induce device deterioration and subsequent reliability problems. By nitrogen concentrations split experiment in thesis，increase of nitrogen concentration is good for blocking boron penetration and also improves reduction of equivalent oxide thickness (EOT). But it would raise gate leak current around 30%，and also lower TDDB and NBTI lifetime around 70-90%. Besides，TDDB results show NMOS lifetime is longer than PMOS lifetime. Until nitrogen concentration reach 14.3%，NMOS and PMOS lifetime will occur smaller gap. The hints are able to explain that NMOS lifetime is affected by nitrogen concentration but PMOS is affected by nitrogen concentration and Boron penetration. By relationship between reliability lifetime and nitrogen concentration，SPA(slot plane antenna) plasma nitridation technology can be estimated limitation of nitrided-oxide for 10 years product warranty.中文摘要-------------------------------------------------I 英文摘要------------------------------------------------II 總目次-------------------------------------------------III 圖目次--------------------------------------------------VI 表目次--------------------------------------------------XI 第一章 序論 1-1前言--------------------------------------------------1 1-2奈米元件技術之挑戰------------------------------------1 1-3研究動機與目的----------------------------------------3 第二章 文獻回顧與理論背景 2-1閘極氧化層缺陷及介面電荷------------------------------5 2-2金氧半二極體電容--------------------------------------7 2-2-1電容操作模型----------------------------------------7 2-2-2電容與頻率關係--------------------------------------7 2-3金氧半場效電晶體操作原理-----------------------------10 2-3-1臨界電壓VT-----------------------------------------10 2-3-2汲極電流(Id)與電壓(Vd)輸出特性---------------------11 2-4 氧化層時間相關崩潰效應(TDDB)------------------------13 2-5 負偏壓溫度不穩定效應(NBTI)--------------------------16 2-6 韋伯分佈--------------------------------------------18 第三章 實驗步驟與方法 3-1 試片前處理------------------------------------------19 3-1-1金氧半元件製作-------------------------------------19 3-1-2測試鍵(Test Key)種類及佈局-------------------------21 3-2 實驗設備--------------------------------------------22 3-3 實驗流程--------------------------------------------24 3-3-1實驗流程說明---------------------------------------24 3-3-2 SPA氧化層氮化濃度樣品製備-------------------------24 3-3-3 MOSFET與MOS特性量測-------------------------------26 3-3-4 元件可靠度TDDB與NBTI量測--------------------------26 3-4 實驗分析儀器----------------------------------------30 第四章 結果與討論 4-1電容-電壓曲線與氧化層氮化濃度關係--------------------32 4-2電流密度-電壓曲線與氧化層氮化濃度關係----------------35 4-3 MOSFET Id-Vg曲線與氧化層氮化濃度關係----------------38 4-4 TDDB Lifetime與氧化層氮化濃度關係-------------------41 4-5 NBTI Lifetime與氧化層氮化濃度關係-------------------53 第五章 結論------------------------------------------- 60 參考文獻----------------------------------------------- 6