Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes

Bidirectional neural interfaces are tools designed to “communicate” with the brain via recording and modulation of neuronal activity. The bidirectional interface systems have been adopted for many applications. Neuroscientists employ them to map neuronal circuits through precise stimulation and recording. Medical doctors deploy them as adaptable medical devices which control therapeutic stimulation parameters based on monitoring real-time neural activity. Brain-machine-interface (BMI) researchers use neural interfaces to bypass the nervous system and directly control neuroprosthetics or brain-computer-interface (BCI) spellers. In bidirectional interfaces, the implantable transducers as well as the corresponding electronic circuits and systems face several challenges. A high channel count, low power consumption, and reduced system size are desirable for potential chronic deployment and wider applicability. Moreover, a neural interface designed for robust closed-loop operation requires the mitigation of stimulation artifacts which corrupt the recorded signals. This dissertation introduces several techniques targeting low power consumption, small size, and reduction of stimulation artifacts. These techniques are implemented for extracellular electrophysiological recording and two stimulation modalities: direct current stimulation for closed-loop control of seizure detection/quench and optical stimulation for optogenetic studies. While the two modalities differ in their mechanisms, hardware implementation, and applications, they share many crucial system-level challenges. The first method aims at solving the critical issue of stimulation artifacts saturating the preamplifier in the recording front-end. To prevent saturation, a novel mixed-signal stimulation artifact cancellation circuit is devised to subtract the artifact before amplification and maintain the standard input range of a power-hungry preamplifier. Additional novel techniques have been also implemented to lower the noise and power consumption. A common average referencing (CAR) front-end circuit eliminates the cross-channel common mode noise by averaging and subtracting it in analog domain. A range-adapting SAR ADC saves additional power by eliminating unnecessary conversion cycles when the input signal is small. Measurements of an integrated circuit (IC) prototype demonstrate the attenuation of stimulation artifacts by up to 42 dB and cross-channel noise suppression by up to 39.8 dB. The power consumption per channel is maintained at 330 nW, while the area per channel is only 0.17 mm2. The second system implements a compact headstage for closed-loop optogenetic stimulation and electrophysiological recording. This design targets a miniaturized form factor, high channel count, and high-precision stimulation control suitable for rodent in-vivo optogenetic studies. Monolithically integrated optoelectrodes (which include 12 µLEDs for optical stimulation and 12 electrical recording sites) are combined with an off-the-shelf recording IC and a custom-designed high-precision LED driver. 32 recording and 12 stimulation channels can be individually accessed and controlled on a small headstage with dimensions of 2.16 x 2.38 x 0.35 cm and mass of 1.9 g. A third system prototype improves the optogenetic headstage prototype by furthering system integration and improving power efficiency facilitating wireless operation. The custom application-specific integrated circuit (ASIC) combines recording and stimulation channels with a power management unit, allowing the system to be powered by an ultra-light Li-ion battery. Additionally, the µLED drivers include a high-resolution arbitrary waveform generation mode for shaping of µLED current pulses to preemptively reduce artifacts. A prototype IC occupies 7.66 mm2, consumes 3.04 mW under typical operating conditions, and the optical pulse shaping scheme can attenuate stimulation artifacts by up to 3x with a Gaussian-rise pulse rise time under 1 ms.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147674/1/mendrela_1.pd

Embedded Electronic Systems for Electronic Skin Applications

The advances in sensor devices are potentially providing new solutions to many applications including prosthetics and robotics. Endowing upper limb prosthesis with tactile sensors (electronic/sensitive skin) can be used to provide tactile sensory feedback to the amputees. In this regard, the prosthetic device is meant to be equipped with tactile sensing system allowing the user limb to receive tactile feedback about objects and contact surfaces. Thus, embedding tactile sensing system is required for wearable sensors that should cover wide areas of the prosthetics. However, embedding sensing system involves set of challenges in terms of power consumption, data processing, real-time response and design scalability (e-skin may include large number of tactile sensors). The tactile sensing system is constituted of: (i) a tactile sensor array, (ii) an interface electronic circuit, (iii) an embedded processing unit, and (iv) a communication interface to transmit tactile data. The objective of the thesis is to develop an efficient embedded tactile sensing system targeting e-skin application (e.g. prosthetic) by: 1) developing a low power and miniaturized interface electronics circuit, operating in real-time; 2) proposing an efficient algorithm for embedded tactile data processing, affecting the system time latency and power consumption; 3) implementing an efficient communication channel/interface, suitable for large amount of data generated from large number of sensors. Most of the interface electronics for tactile sensing system proposed in the literature are composed of signal conditioning and commercial data acquisition devices (i.e. DAQ). However, these devices are bulky (PC-based) and thus not suitable for portable prosthetics from the size, power consumption and scalability point of view. Regarding the tactile data processing, some works have exploited machine learning methods for extracting meaningful information from tactile data. However, embedding these algorithms poses some challenges because of 1) the high amount of data to be processed significantly affecting the real time functionality, and 2) the complex processing tasks imposing burden in terms of power consumption. On the other hand, the literature shows lack in studies addressing data transfer in tactile sensing system. Thus, dealing with large number of sensors will pose challenges on the communication bandwidth and reliability. Therefore, this thesis exploits three approaches: 1) Developing a low power and miniaturized Interface Electronics (IE), capable of interfacing and acquiring signals from large number of tactile sensors in real-time. We developed a portable IE system based on a low power arm microcontroller and a DDC232 A/D converter, that handles an array of 32 tactile sensors. Upon touch applied to the sensors, the IE acquires and pre-process the sensor signals at low power consumption achieving a battery lifetime of about 22 hours. Then we assessed the functionality of the IE by carrying out Electrical and electromechanical characterization experiments to monitor the response of the interface electronics with PVDF-based piezoelectric sensors. The results of electrical and electromechanical tests validate the correct functionality of the proposed system. In addition, we implemented filtering methods on the IE that reduced the effect of noise in the system. Furthermore, we evaluated our proposed IE by integrating it in tactile sensory feedback system, showing effective deliver of tactile data to the user. The proposed system overcomes similar state of art solutions dealing with higher number of input channels and maintaining real time functionality. 2) Optimizing and implementing a tensorial-based machine learning algorithm for touch modality classification on embedded Zynq System-on-chip (SoC). The algorithm is based on Support Vector Machine classifier to discriminate between three input touch modality classes \u201cbrushing\u201d, \u201crolling\u201d and \u201csliding\u201d. We introduced an efficient algorithm minimizing the hardware implementation complexity in terms of number of operations and memory storage which directly affect time latency and power consumption. With respect to the original algorithm, the proposed approach \u2013 implemented on Zynq SoC \u2013 achieved reduction in the number of operations per inference from 545 M-ops to 18 M-ops and the memory storage from 52.2 KB to 1.7 KB. Moreover, the proposed method speeds up the inference time by a factor of 43 7 at a cost of only 2% loss in accuracy, enabling the algorithm to run on embedded processing unit and to extract tactile information in real-time. 3) Implementing a robust and efficient data transfer channel to transfer aggregated data at high transmission data rate and low power consumption. In this approach, we proposed and demonstrated a tactile sensory feedback system based on an optical communication link for prosthetic applications. The optical link features a low power and wide transmission bandwidth, which makes the feedback system suitable for large number of tactile sensors. The low power transmission is due to the employed UWB-based optical modulation. We implemented a system prototype, consisting of digital transmitter and receiver boards and acquisition circuits to interface 32 piezoelectric sensors. Then we evaluated the system performance by measuring, processing and transmitting data of the 32 piezoelectric sensors at 100 Mbps data rate through the optical link, at 50 pJ/bit communication energy consumption. Experimental results have validated the functionality and demonstrated the real time operation of the proposed sensory feedback system

Wired, wireless and wearable bioinstrumentation for high-precision recording of bioelectrical signals in bidirectional neural interfaces

It is widely accepted by the scientific community that bioelectrical signals, which can be used for the identification of neurophysiological biomarkers indicative of a diseased or pathological state, could direct patient treatment towards more effective therapeutic strategies. However, the design and realisation of an instrument that can precisely record weak bioelectrical signals in the presence of strong interference stemming from a noisy clinical environment is one of the most difficult challenges associated with the strategy of monitoring bioelectrical signals for diagnostic purposes. Moreover, since patients often have to cope with the problem of limited mobility being connected to bulky and mains-powered instruments, there is a growing demand for small-sized, high-performance and ambulatory biopotential acquisition systems in the Intensive Care Unit (ICU) and in High-dependency wards. Furthermore, electrical stimulation of specific target brain regions has been shown to alleviate symptoms of neurological disorders, such as Parkinson’s disease, essential tremor, dystonia, epilepsy etc. In recent years, the traditional practice of continuously stimulating the brain using static stimulation parameters has shifted to the use of disease biomarkers to determine the intensity and timing of stimulation. The main motivation behind closed-loop stimulation is minimization of treatment side effects by providing only the necessary stimulation required within a certain period of time, as determined from a guiding biomarker. Hence, it is clear that high-quality recording of local field potentials (LFPs) or electrocorticographic (ECoG) signals during deep brain stimulation (DBS) is necessary to investigate the instantaneous brain response to stimulation, minimize time delays for closed-loop neurostimulation and maximise the available neural data. To our knowledge, there are no commercial, small, battery-powered, wearable and wireless recording-only instruments that claim the capability of recording ECoG signals, which are of particular importance in closed-loop DBS and epilepsy DBS. In addition, existing recording systems lack the ability to provide artefact-free high-frequency (> 100 Hz) LFP recordings during DBS in real time primarily because of the contamination of the neural signals of interest by the stimulation artefacts. To address the problem of limited mobility often encountered by patients in the clinic and to provide a wide variety of high-precision sensor data to a closed-loop neurostimulation platform, a low-noise (8 nV/√Hz), eight-channel, battery-powered, wearable and wireless multi-instrument (55 × 80 mm2) was designed and developed. The performance of the realised instrument was assessed by conducting both ex vivo and in vivo experiments. The combination of desirable features and capabilities of this instrument, namely its small size (~one business card), its enhanced recording capabilities, its increased processing capabilities, its manufacturability (since it was designed using discrete off-the-shelf components), the wide bandwidth it offers (0.5 – 500 Hz) and the plurality of bioelectrical signals it can precisely record, render it a versatile tool to be utilized in a wide range of applications and environments. Moreover, in order to offer the capability of sensing and stimulating via the same electrode, novel real-time artefact suppression methods that could be used in bidirectional (recording and stimulation) system architectures are proposed and validated. More specifically, a novel, low-noise and versatile analog front-end (AFE), which uses a high-order (8th) analog Chebyshev notch filter to suppress the artefacts originating from the stimulation frequency, is presented. After defining the system requirements for concurrent LFP recording and DBS artefact suppression, the performance of the realised AFE is assessed by conducting both in vitro and in vivo experiments using unipolar and bipolar DBS (monophasic pulses, amplitude ranging from 3 to 6 V peak-to-peak, frequency 140 Hz and pulse width 100 µs). Under both in vitro and in vivo experimental conditions, the proposed AFE provided real-time, low-noise and artefact-free LFP recordings (in the frequency range 0.5 – 250 Hz) during stimulation. Finally, a family of tunable hardware filter designs and a novel method for real-time artefact suppression that enables wide-bandwidth biosignal recordings during stimulation are also presented. This work paves the way for the development of miniaturized research tools for closed-loop neuromodulation that use a wide variety of bioelectrical signals as control signals.Open Acces

A Neural Signal Processor for Low-Latency Spike Inference

This thesis describes the development of a system that can assign identities to a population of single-units, in multi-electrode recordings, at single-spike resolution with low-latency. The system has two parts. The first is a Field-Programmable Gate Array (FPGA)-based Neural Signal Processor (NSP) that receives raw input and generates labelled spikes as output, a process referred to as real-time spike inference. The second is a piece of software (Spiketag) that runs on a PC, communicates with the NSP, and generates a spike-sorted model to guide the real-time spike inference. The NSP provides clocks and control signals to five 32-channel INTAN RHD2132 chips to manage the acquisition of 160 channels of raw neural data. In parallel, the NSP further filters, detects and extracts extracellular spike waveforms from the raw neural data recorded by tetrodes or silicon probes and assigns single-unit identity to each detected spike. A set of Python application programming interfaces (APIs) was developed in Spiketag to enable the communication between the NSP and the PC. These APIs allow the NSP to obtain a model from the PC, which holds parameters such as reference channels, spike detection thresholds, spike feature transformation matrix and vector quantized clusters generated by spike sorting a short recording session. Using the spike-sorted model, the NSP performs data acquisition and real-time spike inference simultaneously. Algorithmic modules were implemented in the FPGA and pipelined to compute during 40 ms acquisition intervals. At the output end of the FPGA NSP, the real-time assigned single-unit identity (spike-id) is packaged with the timestamp, the electrode group, and the spike features as a spike-id packet. Spike-id packets are asynchronously transmitted through a low-latency Peripheral Component Interconnect Express (PCIe) interface to the PC, producing the real-time spike trains. The real-time spike trains can be used for further processing, such as real-time decoding. Several types of ground-truth data, including intracellular/extracellular paired recordings, synthesized tetrode extracellular waveforms with ground-truth spike timing and high-channel-count silicon probe recordings with ground-truth animal positions during navigation were used to validate the low-latency (1 ms) and high-accuracy (as high as state-of-the-art offline sorting and decoding algorithms) of the NSP’s real-time spike inference and the NSP-based real-time population decoding performance

High-speed Time-interleaved Digital-to-Analog Converter (TI-DAC) for Self-Interference Cancellation Applications

Nowadays, the need for higher data-rate is constantly growing to enhance the quality of the daily communication services. The full-duplex (FD) communication is exemplary method doubling the data-rate compared to half-duplex one. However, part of the strong output signal of the transmitter interferes to the receiver-side because they share the same antenna with limited attenuation and, as a result, the receiver’s performance is corrupted. Hence, it is critical to remove the leakage signal from the receiver’s path by designing another block called self-interference cancellation (SIC). The main goal of this dissertation is to develop the SIC block embedded in the current-mode FD receivers. To this end, the regenerated cancellation current signal is fed to the inputs of the base-band filter and after the mixer of a (direct-conversion) current-mode FD receiver. Since the pattern of the transmitter (the digital signal generated by DSP) is known, a high-speed digital-to-Analog converter (DAC) with medium-resolution can perfectly suppress main part of the leakage on the receiver path. A capacitive DAC (CDAC) is chosen among the available solutions because it is compatible with advanced CMOS technology for high-speed application and the medium-resolution designs. Although the main application of the design is to perform the cancellation, it can also be employed as a stand-alone DAC in the Analog (I/Q) transmitter. The SIC circuitry includes a trans-impedance amplifier (TIA), two DACs, high-speed digital circuits, and built-in-self-test section (BIST). According to the available specification for full-duplex communication system, the resolution and working frequency of the CDAC are calculated (designed) equal to 10-bit (3 binary+ 2 binary + 5 thermometric) and 1GHz, respectively. In order to relax the design of the TIA (settling time of the DAC), the CDAC implements using 2-way time-interleaved (TI) manner (the effective SIC frequency equals 2GHz) without using any calibration technique. The CDAC is also developed with the split-capacitor technique to lower the negative effects of the conventional binary-weighted DAC. By adding one extra capacitor on the left-side of the split-capacitor, LSB-side, the value of the split-capacitor can be chosen as an integer value of the unit capacitor. As a result, it largely enhances the linearity of the CADC and cancellation performance. If the block works as a stand-alone DAC with non-TI mode, the digital input code representing a Sinus waveform with an amplitude 1dB less than full-scale and output frequency around 10.74MHz, chosen by coherent sampling rule, then the ENOB, SINAD, SFDR, and output signal are 9.4-bit, 58.2 dB, 68.4dBc, and -9dBV. The simulated value of the |DNL| (static linearity) is also less than 0.7. The similar simulation was done in the SIC mode while the capacitive-array woks in the TI mode and cancellation current is set to the full-scale. Hence, the amount of cancelling the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. equals 51.3dB, 15.1 dB, 24dBc, 66.4 dB. The designed SIC cannot work as a closed-loop design. The layout was optimally drawn in order to minimize non-linearity, the power-consumption of the decoders, and reduce the complexity of the DAC. By distributing the thermometric cells across the array and using symmetrical switching scheme, the DAC is less subjected to the linear and gradient effect of the oxide. Based on the post-layout simulation results, the deviation of the design after drawing the layout is studied. To compare the results of the schematic and post-layout designs, the exact conditions of simulation above (schematic simulations) are used. When the block works as a stand-alone CDAC, the ENOB, SINAD, SFDR are 8.5-bit, 52.6 dB, 61.3 dBc. The simulated value of the |DNL| (static linearity) is also limited to 1.3. Likewise, the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. are equal to 44dB, 11.7 dB, 19 dBc, 55.7 dB

A Closed-Loop Deep Brain Stimulation Device With a Logarithmic Pipeline ADC.

This dissertation is a summary of the research on integrated closed-loop deep brain stimulation for treatment of Parkinson’s disease. Parkinson's disease is a progressive disorder of the central nervous system affecting more than three million people in the United States. Deep Brain Stimulation (DBS) is one of the most effective treatments of Parkinson’s symptoms. DBS excites the Subthalamic Nucleus (STN) with a high frequency electrical signal. The proposed device is a single-chip closed-loop DBS (CDBS) system. Closed-loop feedback of sensed neural activity promises better control and optimization of stimulation parameters than with open-loop devices. Thanks to a novel architecture, the prototype system incorporates more functionality yet consumes less power and area compared to other systems. Eight front-end low-noise neural amplifiers (LNAs) are multiplexed to a single high-dynamic-range logarithmic, pipeline analog-to-digital converter (ADC). To save area and power consumption, a high dynamic-range log ADC is used, making analog automatic gain control unnecessary. The redundant 1.5b architecture relaxes the requirements for the comparator accuracy and comparator reference voltage accuracy. Instead of an analog filter, an on-chip digital filter separates the low frequency neural field potential signal from the neural spike energy. An on-chip controller generates stimulation patterns to control the 64 on-chip current-steering DACs. The 64 DACs are formed as a cascade of a single shared 2-bit coarse current DAC and 64 individual bi-directional 4-bit fine DACs. The coarse/fine configuration saves die area since the MSB devices tend to be large. Real-time neural activity was recorded with the prototype device connected to microprobes that were chronically implanted in two Long Evans rats. The recorded in-vivo signal clearly shows neural spikes of 10.2 dB signal-to-noise ratio (SNR) as well as a periodic artifact from neural stimulation. The recorded neural information has been analyzed with single unit sorting and principal component analysis (PCA). The PCA scattering plots from multi-layers of cortex represent diverse information from either single or multiple neural sources. The single-unit neural sorting analysis along with PCA verifies the feasibility of the implantable CDBS device for to in-vivo neural recording interface applications.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/60733/1/milaca_1.pd

Detecting and locating electronic devices using their unintended electromagnetic emissions

Electronically-initiated explosives can have unintended electromagnetic emissions which propagate through walls and sealed containers. These emissions, if properly characterized, enable the prompt and accurate detection of explosive threats. The following dissertation develops and evaluates techniques for detecting and locating common electronic initiators. The unintended emissions of radio receivers and microcontrollers are analyzed. These emissions are low-power radio signals that result from the device\u27s normal operation. In the first section, it is demonstrated that arbitrary signals can be injected into a radio receiver\u27s unintended emissions using a relatively weak stimulation signal. This effect is called stimulated emissions. The performance of stimulated emissions is compared to passive detection techniques. The novel technique offers a 5 to 10 dB sensitivity improvement over passive methods for detecting radio receivers. The second section develops a radar-like technique for accurately locating radio receivers. The radar utilizes the stimulated emissions technique with wideband signals. A radar-like system is designed and implemented in hardware. Its accuracy tested in a noisy, multipath-rich, indoor environment. The proposed radar can locate superheterodyne radio receivers with a root mean square position error less than 5 meters when the SNR is 15 dB or above. In the third section, an analytic model is developed for the unintended emissions of microcontrollers. It is demonstrated that these emissions consist of a periodic train of impulses. Measurements of an 8051 microcontroller validate this model. The model is used to evaluate the noise performance of several existing algorithms. Results indicate that the pitch estimation techniques have a 4 dB sensitivity improvement over epoch folding algorithms --Abstract, page iii

12.8 kHz Energy-Efficient Read-Out IC for High Precision Bridge Sensor Sensing System

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 김수환.In the thesis, a high energy-efficient read-out integrated circuit (read-out IC) for a high-precision bridge sensor sensing system is proposed. A low-noise capacitively-coupled chopper instrumentation amplifier (CCIA) followed by a high-resolution incremental discrete-time delta-sigma modulator (DTΔΣΜ) analog-to-digital converter (ADC) is implemented. To increase energy-efficiency, CCIA is chosen, which has the highest energy-efficiency among IA types. CCIA has a programmable gain of 1 to 128 that can amplify the small output of the bridge sensor. Impedance boosting loop (IBL) is applied to compensate for the low input impedance, which is a disadvantage of a CCIA. Also, the sensor offset cancellation technique was applied to CCIA to eliminate the offset resulting from the resistance mismatch of the bridge sensor, and the bridge sensor offset from -350 mV to 350 mV can be eliminated. In addition, the output data rate of the read-out IC is designed to be 12.8 kHz to quickly capture data and to reduce the power consumption of the sensor by turning off the sensor and read-out IC for the rest of the time. Generally, bridge sensor system is much slower than 12.8 kHz. To suppress 1/f noise, system level chopping and correlated double sampling (CDS) techniques are used. Implemented in a standard 0.13-μm CMOS process, the ROIC’s effective resolution is 17.0 bits at gain 1 and that of 14.6 bits at gain 128. The analog part draws the average current of 139.4 μA from 3-V supply, and 60.2 μA from a 1.8 V supply.본 논문에서는 고정밀 브리지 센서 센싱 시스템을 위한 에너지 효율이 높은 Read-out Integrated Circuit (read-out IC)를 제안한다. 저 잡음 Capacitively-Coupled Instrumentation Amplifier (CCIA)에 이은 고해상도 Discrete-time Delta-Sigma 변조기(DTΔΣΜ) 아날로그-디지털 변환기(ADC)를 구현하였다. 에너지 효율을 높이기 위해 IA 유형 중 에너지 효율이 가장 높은 CCIA를 선택하였다. CCIA는 브리지 센서의 작은 출력을 증폭할 수 있는 1 에서 128의 프로그래밍 가능한 전압 이득을 가진다. CCIA의 단점인 낮은 입력 임피던스를 보상하기 위해 Impedance Boosting Loop (IBL)을 적용하였다. 또한 CCIA에 센서 오프셋 제거 기술을 적용하여 브리지 센서의 저항 미스매치로 인한 오프셋을 제거 기능을 탑재하였으며 -350mV에서 350mV까지 브리지 센서 오프셋을 제거할 수 있다. Read-out IC의 출력 데이터 전송률은 12.8kHz로 설계하여 데이터를 빠르게 채고 나머지 시간 동안 센서와 read-out IC를 꺼서 센서의 전력 소비를 줄일 수 있도록 설계하였다. 일반적으로 브리지 센서 시스템은 12.8kHz보다 느리기 때문에 이것이 가능하다. 하지만, 일반적인 CCIA는 입력 임피던스 때문에 빠른 속도에서 설계가 불가능하다. 이를 해결하기 위해 demodulate 차핑을 앰프 내부가 아닌 시스템 차핑을 이용해 해결하였다. 1/f 노이즈를 억제하기 위해 시스템 레벨 차핑 및 상관 이중 샘플링(CDS) 기술이 사용되었다. 0.13μm CMOS 공정에서 구현된 read-out IC의 Effective Resolution (ER)은 전압 이득 1에서 17.0비트이고 전압 이득 128에서 14.6비트를 달성하였다. 아날로그 회로는 3 V 전원에서 139.4μA의 평균 전류를, 디지털 회로는 1.8 V 전원에서 60.2μA의 평균 전류를 사용한다.CHAPTER 1 INTRODUCTION 1 1.1 SMART DEVICES 1 1.2 SMART SENSOR SYSTEMS 4 1.3 WHEATSTONE BRIDGE SENSOR 5 1.4 MOTIVATION 8 1.5 PREVIOUS WORKS 10 1.6 INTRODUCTION OF THE PROPOSED SYSTEM 14 1.7 THESIS ORGANIZATION 16 CHAPTER 2 SYSTEM OVERVIEW 17 2.1 SYSTEM ARCHITECTURE 17 CHAPTER 3 IMPLEMENTATION OF THE CCIA 19 3.1 CAPACITIVELY-COUPLED CHOPPER INSTRUMENTATION AMPLIFIER 19 3.2 IMPEDANCE BOOSTING 22 3.3 SENSOR OFFSET CANCELLATION 25 3.4 AMPLIFIER OFFSET CANCELLATION 29 3.5 AMPLIFIER IMPLEMENTATION 32 3.6 IMPLEMENTATION OF THE CCIA 35 CHAPTER 4 INCREMENTAL ΔΣ ADC 37 4.1 INTRODUCTION OF INCREMENTAL ΔΣ ADC 37 4.2 IMPLEMENTATION OF INCREMENTAL ΔΣ MODULATOR 40 CHAPTER 5 SYSTEM-LEVEL DESIGN 43 5.1 DIGITAL FILTER 43 5.2 SYSTEM-LEVEL CHOPPING & TIMING 46 CHAPTER 5 MEASUREMENT RESULTS 48 6.1 MEASUREMENT SUMMARY 48 6.2 LINEARITY & NOISE MEASUREMENT 51 6.3 SENSOR OFFSET CANCELLATION MEASUREMENT 57 6.4 INPUT IMPEDANCE MEASUREMENT 59 6.5 TEMPERATURE VARIATION MEASUREMENT 63 6.6 PERFORMANCE SUMMARY 66 CHAPTER 7 CONCLUSION 68 APPENDIX A. 69 ENERGY-EFFICIENT READ-OUT IC FOR HIGH-PRECISION DC MEASUREMENT SYSTEM WITH IA POWER REDUCTION TECHNIQUE 69 BIBLIOGRAPHY 83 한글초록 87박