82 research outputs found
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Fully-passive switched-capacitor techniques for high performance SAR ADC design
In recent years, SAR ADC becomes more and more popular in various low-power applications such as wireless sensors and low energy radios due to its circuit simplicity, high power efficiency, and scaling compatibility. However, its speed is limited by its successive approximation procedures and its power efficiency greatly reduces with the ADC resolution going beyond 10 bit. To address these issues, this thesis proposes to embed two techniques: 1) compressive sensing (CS) and 2) noise shaping (NS) to a conventional SAR ADC. The realization of both techniques are based on fully-passive switched-capacitor techniques.
CS is a recently emerging sampling paradigm, stating that the sparsity of a signal can be exploited to reduce the ADC sampling rate below the Nyquist rate. Different from conventional CS frameworks which require dedicated analog CS encoders, this thesis proposes a fully-passive CS-SAR ADC architecture which only requires minor modification to a conventional SAR ADC. Two chips are fabricated in a 0.13 µm process to prove the concept. One chip is a single-channel CS-SAR ADC which can reduce the ADC conversion rate by 4 times, thus reducing the ADC power by 4 times. In many wireless sensing applications, multiple ADCs are commonly required to sense multi-channel signals such as multi-lead ECG sensing and parallel neural recording. Therefore, the other chip is a multi-channel CS-SAR ADC which can simultaneously convert 4-channel signals with a sampling rate of one channel’s Nyquist rate. At 0.8 V and 1 MS/s, both chips achieve an effective Walden FoM of around 5 fJ/conversion-step.
This thesis also proposes a novel NS SAR ADC architecture that is simple, robust and low power for high-resolution applications. Compared to conventional ∆Σ ADCs, it replaces the power-hungry active integrator with a passive integrator which only requires one switch and two capacitors. Compared to previous 1st-order NS SAR ADC works, it achieves the best NS performance and can be easily extended to 2nd-order. A 1st-order 10-bit NS SAR ADC is fabricated in a 0.13 µm process. Through NS, SNDR increases by 6 dB with OSR doubled, achieving a 12- bit ENOB at OSR = 8. An improved version of a 2nd-order 9-bit NS SAR ADC is designed and simulated in a 40 nm process. The SNDR increases by 10 dB with OSR doubled, achieving a 14-bit ENOB at OSR = 16. At a bandwidth of 312.5 kHz, the Schreier FoM is 181 dB and the Walden FoM is 12.5 fJ/conversion-step, proving that the proposed NS SAR ADC architecture can achieve high resolution and high power efficiency simultaneously.Electrical and Computer Engineerin
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Signal acquisition challenges in mobile systems
In recent decades, the advent of mobile computing has changed human lives by providing information that was not available in the past. The mobile computing platform opens a new door to the connected world in which various forms of hand-held and wearable systems are ubiquitous. A single mobile device plays multiple roles and shapes human lives towards a better future. In these systems, sensor-based data acquisition plays an essential role in generating and providing useful information.
The increased number of sensors is embedded in a single device in order to process various signal modalities. In practice, more than 30 data converters are required in designing a mobile system in which the data-converting blocks become among the most power-hungry components in battery-operated systems. Due to the increased variety of sensors, mobile systems are meant to face several obstacles. For example, the increased number of sensors increase system power consumption during the system operation. The increased power consumption directly affects operation time because mobile systems are powered by a limited energy source. Moreover, an increased amount of information also gives rise to bandwidth problems in communication due to the increased volume of data transmission. Also, this system design requires a larger area in a silicon die so that multiple signal paths can be placed without cross-channel interference. Therefore, the system design has presented a challenge in terms of trying to resolve the design constraints such as power consumption, bandwidth usage, storage space, and design complexity issues.
To overcome these obstacles, in this dissertation, efficient data acquisition and processing methods are investigated. Specifically, this thesis considers the problems of energy-efficient sampling and binary event detection.
This dissertation begins by presenting a new signal sampling scheme that enables higher precision signal conversion in compressed-sensing-based signal acquisition. The proposed scheme is based on the popular successive approximation register and employs a modified compressive sensing technique to increase the resolution of successive-approximation-register (SAR) analog-to-digital converter (ADC) architecture. Circuit-level architecture is discussed to implement the proposed scheme using the SAR ADC architecture. A non-uniform quantization scheme is proposed and it improves data quality after data acquisition. The proposed scheme is expected to be used for medium- or high- frequency data conversion.
Secondly, the possibility of using fewer ADCs than channels is studied by leveraging sparse-signal representation and blind-source-separation (BSS) techniques.
In particular, this dissertation examines the problem of using a single ADC or quantizer system for digitizing multi-channel inputs. Mixing and de-mixing strategies are extensively studied for sampling frequency-sparse signals and the proposed multi-channel architecture can be easily implemented using today's analog/mixed-signal circuits.
The third part of this dissertation investigates a binary hypothesis testing problem. In mobile devices such as smartphones and tablet PCs, a major portion of energy is consumed in user interfaces (LCD display and touch input processing). For accurate detection and better user interface, energy-efficient sensing and detection schemes are necessary to manage multiple sensor inputs. A highly efficient detection scheme is presented that can detect binary events reliably with a fraction of the energy consumption required in the conventional energy detection.Electrical and Computer Engineerin
Sparsity-Aware Low-Power ADC Architecture with Advanced Reconstruction Algorithms
Compressive sensing (CS) technique enables a universal sub-Nyquist sampling of sparse and compressible signals, while still guaranteeing the reliable signal recovery. Its potential lies in the reduced analog-to-digital conversion rate in sampling broadband and/or multi-channel sparse signals, where conventional Nyquist-rate sampling are either technology impossible or extremely hardware costly.
Nevertheless, there are many challenges in the CS hardware design. In coherent sampling, state-of-the-art mixed-signal CS front-ends, such as random demodulator and modulated wideband converter, suffer from high power and nonlinear hardware. In signal recovery, state-of-the-art CS reconstruction methods have tractable computational complexity and probabilistically guaranteed performance. However, they are still high cost (basis pursuit) or noise sensitive (matching pursuit).
In this dissertation, we propose an asynchronous compressive sensing (ACS) front-end and advanced signal reconstruction algorithms to address these challenges. The ACS front-end consists of a continuous-time ternary encoding (CT-TE) scheme which converts signal amplitude variations into high-rate ternary timing signal, and a digital random sampler (DRS) which captures the ternary timing signal at sub-Nyquist rate. The CT-TE employs asynchronous sampling mechanism for pulsed-like input and has signal-dependent conversion rate. The DRS has low power, ease of massive integration, and excellent linearity in comparison to state-of-the-art mixed-signal CS front-ends.
We propose two reconstruction algorithms. One is group-based total variation, which exploits piecewise-constant characteristics and achieves better mean squared error and faster convergence rate than the conventional TV scheme with moderate noise. The second algorithm is split-projection least squares (SPLS), which relies on a series of low-complexity and independent l2-norm problems with the prior on ternary-valued signal. The SPLS scheme has good noise robustness, low-cost signal reconstruction and facilitates a parallel hardware for real-time signal recovery.
In application study, we propose multi-channel filter banks ACS front-end for the interference-robust radar. The proposed receiver performs reliable target detection with nearly 8-fold data compression than Nyquist-rate sampling in the presence of -50dBm wireless interference. We also propose an asynchronous compressed beamformer (ACB) for low-power portable diagnostic ultrasound. The proposed ACB achieves 9-fold data volume compression and only 4.4% contrast-to-noise ratio loss on the imaging results when compared with the Nyquist-rate ADCs
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