Optimal ILP-Based Approach for Gate Location Assignment and Scheduling in Quantum Circuits

Physical design and synthesis are two key processes of quantum circuit design methodology. The physical design process itself decomposes into scheduling, mapping, routing, and placement. In this paper, a mathematical model is proposed for mapping, routing, and scheduling in ion-trap technology in order to minimize latency of the circuit. The proposed model which is a mixed integer linear programming (MILP) model gives the optimal locations for gates and the best sequence of operations in terms of latency. Experimental results show that our scheme outperforms the other schemes for the attempted benchmarks

Tight Bounds on the Synthesis of 3-bit Reversible Circuits: NFT Library

The reversible circuit synthesis problem can be reduced to permutation group. This allows Schreier-Sims Algorithm for the strong generating set-finding problem to be used to find tight bounds on the synthesis of 3-bit reversible circuits using the NFT library. The tight bounds include the maximum and minimum length of 3-bit reversible circuits, the maximum and minimum cost of 3-bit reversible circuits. The analysis shows better results than that found in the literature for the lower bound of the cost. The analysis also shows that there are 1960 universal reversible sub-libraries from the main NFT library.Comment: 18 pages. arXiv admin note: text overlap with arXiv:1101.438

Exact and practical pattern matching for quantum circuit optimization

Quantum computations are typically compiled into a circuit of basic quantum gates. Just like for classical circuits, a quantum compiler should optimize the quantum circuit, e.g. by minimizing the number of required gates. Optimizing quantum circuits is not only relevant for improving the runtime of quantum algorithms in the long term, but is also particularly important for near-term quantum devices that can only implement a small number of quantum gates before noise renders the computation useless. An important building block for many quantum circuit optimization techniques is pattern matching, where given a large and a small quantum circuit, we are interested in finding all maximal matches of the small circuit, called pattern, in the large circuit, considering pairwise commutation of quantum gates. In this work, we present a classical algorithm for pattern matching that provably finds all maximal matches in time polynomial in the circuit size (for a fixed pattern size). Our algorithm works for both quantum and reversible classical circuits. We demonstrate numerically that our algorithm, implemented in the open-source library Qiskit, scales considerably better than suggested by the theoretical worst-case complexity and is practical to use for circuit sizes typical for near-term quantum devices. Using our pattern matching algorithm as the basis for known circuit optimization techniques such as template matching and peephole optimization, we demonstrate a significant (~30%) reduction in gate count for random quantum circuits, and are able to further improve practically relevant quantum circuits that were already optimized with state-of-the-art techniques.Comment: Raban Iten and Romain Moyard contributed equally to this work. Major updates: Added numerical analysis of the pattern matching algorithm; fixed two special cases that were missed by our algorithm and updated the worst-case complexity analysis. 10 pages summary + 23 pages main text + 7 pages appendi

Fault tolerance in reversible logic

In recent years reversible logic has offered a promising alternative to traditional logic circuits. Reversible logic introduces a mechanism which allows theoretically zero energy dissipation by eliminating the possibility of information loss. However, it is also desirable that all computation should ideally be done in a fault tolerant manner. To address this we propose techniques to achieve fault tolerance in reversible logic based on a passive hardware redundancy technique. We propose two new designs for a reversible majority voter circuit that can be used to implement fault masking. Comparisons to existing designs are presented in terms of cost metrics such as gate count, garbage outputs, constant inputs, and quantum cost. Comparative failure probability analysis of the proposed voter circuits is also provided. Simulation results of the voter circuit failure probabilities over different numbers of trials are also presented. Our approach can be used to determine the circuit failure probability by using the gate failure probabilities. The proposed methodology can provide useful information for future reversible gate fabrication and designing future fault tolerant reversible circuits

Synthesis, testing and tolerance in reversible logic

In recent years, reversible computing has established itself as a promising research area and emerging technology. This thesis focuses on three important areas of reversible logic, which is an area of reversible computing. Firstly, this thesis proposes a transformation based synthesis approach for realizing conservative reversible functions using SWAP and Fredkin gates. This thesis also proposes ten templates for optimizing SWAP and Fredkin gates-based reversible circuits. Secondly, this thesis proposes an approach for the design of online testable reversible circuits. A reversible circuit composed of NOT, CNOT and Toffoli gates can be made online testable by adding two sets of CNOT gates and a single parity line. Finally, we have proposed an approach to achieve fault tolerance in reversible circuits. A design of a 3-bit reversible majority voter circuit is presented. This voter circuit can be used to design fault tolerant reversible circuits