12,879 research outputs found
Boolean Satisfiability in Electronic Design Automation
Boolean Satisfiability (SAT) is often used as the underlying model for a significant and increasing number of applications in Electronic Design Automation (EDA) as well as in many other fields of Computer Science and Engineering. In recent years, new and efficient algorithms for SAT have been developed, allowing much larger problem instances to be solved. SAT “packages” are currently expected to have an impact on EDA applications similar to that of BDD packages since their introduction more than a decade ago. This tutorial paper is aimed at introducing the EDA professional to the Boolean satisfiability problem. Specifically, we highlight the use of SAT models to formulate a number of EDA problems in such diverse areas as test pattern generation, circuit delay computation, logic optimization, combinational equivalence checking, bounded model checking and functional test vector generation, among others. In addition, we provide an overview of the algorithmic techniques commonly used for solving SAT, including those that have seen widespread use in specific EDA applications. We categorize these algorithmic techniques, indicating which have been shown to be best suited for which tasks
A Novel SAT-Based Approach to the Task Graph Cost-Optimal Scheduling Problem
The Task Graph Cost-Optimal Scheduling Problem consists in scheduling a certain number of interdependent tasks onto a set of heterogeneous processors (characterized by idle and running rates per time unit), minimizing the cost of the entire process. This paper provides a novel formulation for this scheduling puzzle, in which an optimal solution is computed through a sequence of Binate Covering Problems, hinged within a Bounded Model Checking paradigm. In this approach, each covering instance, providing a min-cost trace for a given schedule depth, can be solved with several strategies, resorting to Minimum-Cost Satisfiability solvers or Pseudo-Boolean Optimization tools. Unfortunately, all direct resolution methods show very low efficiency and scalability. As a consequence, we introduce a specialized method to solve the same sequence of problems, based on a traditional all-solution SAT solver. This approach follows the "circuit cofactoring" strategy, as it exploits a powerful technique to capture a large set of solutions for any new SAT counter-example. The overall method is completed with a branch-and-bound heuristic which evaluates lower and upper bounds of the schedule length, to reduce the state space that has to be visited. Our results show that the proposed strategy significantly improves the blind binate covering schema, and it outperforms general purpose state-of-the-art tool
Counterexample-Preserving Reduction for Symbolic Model Checking
The cost of LTL model checking is highly sensitive to the length of the
formula under verification. We observe that, under some specific conditions,
the input LTL formula can be reduced to an easier-to-handle one before model
checking. In our reduction, these two formulae need not to be logically
equivalent, but they share the same counterexample set w.r.t the model. In the
case that the model is symbolically represented, the condition enabling such
reduction can be detected with a lightweight effort (e.g., with SAT-solving).
In this paper, we tentatively name such technique "Counterexample-Preserving
Reduction" (CePRe for short), and finally the proposed technquie is
experimentally evaluated by adapting NuSMV
The Configurable SAT Solver Challenge (CSSC)
It is well known that different solution strategies work well for different
types of instances of hard combinatorial problems. As a consequence, most
solvers for the propositional satisfiability problem (SAT) expose parameters
that allow them to be customized to a particular family of instances. In the
international SAT competition series, these parameters are ignored: solvers are
run using a single default parameter setting (supplied by the authors) for all
benchmark instances in a given track. While this competition format rewards
solvers with robust default settings, it does not reflect the situation faced
by a practitioner who only cares about performance on one particular
application and can invest some time into tuning solver parameters for this
application. The new Configurable SAT Solver Competition (CSSC) compares
solvers in this latter setting, scoring each solver by the performance it
achieved after a fully automated configuration step. This article describes the
CSSC in more detail, and reports the results obtained in its two instantiations
so far, CSSC 2013 and 2014
Tarmo: A Framework for Parallelized Bounded Model Checking
This paper investigates approaches to parallelizing Bounded Model Checking
(BMC) for shared memory environments as well as for clusters of workstations.
We present a generic framework for parallelized BMC named Tarmo. Our framework
can be used with any incremental SAT encoding for BMC but for the results in
this paper we use only the current state-of-the-art encoding for full PLTL.
Using this encoding allows us to check both safety and liveness properties,
contrary to an earlier work on distributing BMC that is limited to safety
properties only.
Despite our focus on BMC after it has been translated to SAT, existing
distributed SAT solvers are not well suited for our application. This is
because solving a BMC problem is not solving a set of independent SAT instances
but rather involves solving multiple related SAT instances, encoded
incrementally, where the satisfiability of each instance corresponds to the
existence of a counterexample of a specific length. Our framework includes a
generic architecture for a shared clause database that allows easy clause
sharing between SAT solver threads solving various such instances.
We present extensive experimental results obtained with multiple variants of
our Tarmo implementation. Our shared memory variants have a significantly
better performance than conventional single threaded approaches, which is a
result that many users can benefit from as multi-core and multi-processor
technology is widely available. Furthermore we demonstrate that our framework
can be deployed in a typical cluster of workstations, where several multi-core
machines are connected by a network
Incremental bounded model checking for embedded software
Program analysis is on the brink of mainstream usage in embedded systems development. Formal verification of behavioural requirements, finding runtime errors and test case generation are some of the most common applications of automated verification tools based on bounded model checking (BMC). Existing industrial tools for embedded software use an off-the-shelf bounded model checker and apply it iteratively to verify the program with an increasing number of unwindings. This approach unnecessarily wastes time repeating work that has already been done and fails to exploit the power of incremental SAT solving. This article reports on the extension of the software model checker CBMC to support incremental BMC and its successful integration with the industrial embedded software verification tool BTC EMBEDDED TESTER. We present an extensive evaluation over large industrial embedded programs, mainly from the automotive industry. We show that incremental BMC cuts runtimes by one order of magnitude in comparison to the standard non-incremental approach, enabling the application of formal verification to large and complex embedded software. We furthermore report promising results on analysing programs with arbitrary loop structure using incremental BMC, demonstrating its applicability and potential to verify general software beyond the embedded domain
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