Remote capacitive sensing in two-dimension quantum-dot arrays

We investigate gate-defined quantum dots in silicon on insulator nanowire field-effect transistors fabricated using a foundry-compatible fully-depleted silicon-on-insulator (FD-SOI) process. A series of split gates wrapped over the silicon nanowire naturally produces a $2\times n$ bilinear array of quantum dots along a single nanowire. We begin by studying the capacitive coupling of quantum dots within such a 2$\times$2 array, and then show how such couplings can be extended across two parallel silicon nanowires coupled together by shared, electrically isolated, 'floating' electrodes. With one quantum dot operating as a single-electron-box sensor, the floating gate serves to enhance the charge sensitivity range, enabling it to detect charge state transitions in a separate silicon nanowire. By comparing measurements from multiple devices we illustrate the impact of the floating gate by quantifying both the charge sensitivity decay as a function of dot-sensor separation and configuration within the dual-nanowire structure.Comment: 9 pages, 3 figures, 35 cites and supplementar

Pt-based metallization of PMOS devices for the fabrication of monolithic semiconducting/YBa2Cu3O7-d superconducting devices on silicon

Mo, Pt, Pt/Mo and Pt/Ti thin films have been deposited onto Si and SiO2 substrates by RF sputtering and annealed in the YBa2Cu3O7-d growth conditions. The effect of annealing on the sheet resitance of unpatterned layers was measured. A Pt-based multilayered metallization for the PMOS devices was proposed and tested for the monolithic integration of PMOS devices and YBCO sensors on the same silicon substrate. The best results were obtained with a Pt/Ti/Mo-silicide structure showing (0.472 \Omega_{\Box}) interconnect sheet resistivity and $2 \times 10^{-4} \Omega \cdot cm^{2}$ specific contact resistivity after annealing for (60) minutes at (700^{\circ})C in (0.5) mbar O(_{2}) pressure.Comment: 6 pages, accepted for Microelectronic Engineering, elsevie

Mid-infrared Suspended Waveguide Platform and Building Blocks

In this work we present our recent progress in the development of a platform for the mid-infrared wavelength range, based on suspended silicon waveguide with subwavelength metamaterial cladding. The platform has some intrinsic advantages, which make it a very promising candidate for sensing applications in the fingerprint region. Specifically, it can cover the full transparency window of silicon (up to a wavelength of 8 μm), only requires one lithographic etch-step and can be designed for strong light-matter interaction. Design rules, practical aspects of the fabrication process and experimental results of a complete set of elemental building blocks operating at two very different wavelengths, 3.8 μm and 7.67 μm, will be discussed. Propagation losses as low as 0.82 dB/cm at λo=3.8 μm and 3.1 dB/cm at λo=7.67 μm are attained, for the interconnecting waveguides.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

Biallelic and Genome Wide Association Mapping of Germanium Tolerant Loci in Rice (Oryza sativa L.)

Funding: This project was partially funded by a Biotechnology and Biological Sciences Research Council (BBSRC) grant (BB/J003336/1) awarded to AHP. The work was also supported by a self-funded studentship (PT). The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript.Peer reviewedPublisher PD

Perspective of buried oxide thickness variation on triple metal-gate (TMG) recessed-S/D FD-SOI MOSFET

Recently, Fully-Depleted Silicon on Insulator (FD-SOI) MOSFETs have been accepted as a favourable technology beyond nanometer nodes, and the technique of Recessed-Source/Drain (Re-S/D) has made it more immune in regards of various performance factors. However, the proper selection of Buried-Oxide (BOX) thickness is one of the major challenges in the design of FD-SOI based MOS devices in order to suppress the drain electric penetrations across the BOX interface efficiently. In this work, the effect of BOX thickness on the performance of TMG Re-S/D FD-SOI MOSFET has been presented at 60 nm gate length. The perspective of BOX thickness variation has been analysed on the basis of its surface potential profile and the extraction of the threshold voltage by performing two-dimensional numerical simulations. Moreover, to verify the short channel immunity, the impact of gate length scaling has also been discussed. It is found that the device attains two step-up potential profile with suppressed short channel effects. The outcomes reveal that the Drain Induced Barrier Lowering (DIBL) values are lower among conventional SOI MOSFETs. The device has been designed and simulated by using 2D numerical ATLAS Silvaco TCAD simulator

Thermal transport enhancement of hybrid nanocomposites; impact of confined water inside nanoporous silicon

The thermal transport properties of porous silicon and nano-hybrid "porous silicon/water" systems are presented here. The thermal conductivity was evaluated with equilibrium molecular dynamics technique for porous systems made of spherical voids or water-filled cavities. We revealed large thermal conductivity enhancement in the nano-hybrid systems as compared to their dry porous counterparts, which cannot be captured by effective media theory. This rise of thermal conductivity is related to the increases of the specific surface of the liquid/solid interface. We demonstrated that significant difference for more than two folds of thermal conductivity of pristine porous silicon and "porous silicon liquid/composite" is due to the liquid density fluctuation close to "solid/liquid interface" (layering effect). This effect is getting more important for the high specific surface of the interfacial area. Specifically, the enhancement of the effective thermal conductivity is 50 % for specific surface area of 0.3 (1/nm), and it increases further upon the increase of the surface to volume ratio. Our study provides valuable insights into the thermal properties of hybrid liquid/solid nanocomposites and about the importance of confined liquids within nanoporous materials

General Geometric Fluctuation Modeling for Device Variability Analysis

The authors propose a new modeling approach based on the impedance field method (IFM) to analyze the general geometric variations in device simulations. Compared with the direct modeling of multiple variational devices, the proposed geometric variation (GV) model shows a better efficiency thanks to its IFM based nature. Compared with the existing random geometric fluctuation (RGF) model where the noise sources are limited to the interfaces, the present GV model provides better accuracy and wider application areas as it transforms the geometric variation into global mesh deformation and computes the noise sources induced by the geometric variation in the whole simulation domain. GV model also provides great insights into the device by providing the effective noise sources, equation-wise contributions, and sensitivity maps that are useful for device characterization and optimization