28,125 research outputs found
Architectures for block Toeplitz systems
In this paper efficient VLSI architectures of highly concurrent algorithms for the solution of block linear systems with Toeplitz or near-to-Toeplitz entries are presented. The main features of the proposed scheme are the use of scalar only operations, multiplications/divisions and additions, and the local communication which enables the development of wavefront array architecture. Both the mean squared error and the total squared error formulations are described and a variety of implementations are given
Design and Implementation of an RNS-based 2D DWT Processor
No abstract availabl
Implementation of the Trigonometric LMS Algorithm using Original Cordic Rotation
The LMS algorithm is one of the most successful adaptive filtering
algorithms. It uses the instantaneous value of the square of the error signal
as an estimate of the mean-square error (MSE). The LMS algorithm changes
(adapts) the filter tap weights so that the error signal is minimized in the
mean square sense. In Trigonometric LMS (TLMS) and Hyperbolic LMS (HLMS), two
new versions of LMS algorithms, same formulations are performed as in the LMS
algorithm with the exception that filter tap weights are now expressed using
trigonometric and hyperbolic formulations, in cases for TLMS and HLMS
respectively. Hence appears the CORDIC algorithm as it can efficiently perform
trigonometric, hyperbolic, linear and logarithmic functions. While
hardware-efficient algorithms often exist, the dominance of the software
systems has kept those algorithms out of the spotlight. Among these hardware-
efficient algorithms, CORDIC is an iterative solution for trigonometric and
other transcendental functions. Former researches worked on CORDIC algorithm to
observe the convergence behavior of Trigonometric LMS (TLMS) algorithm and
obtained a satisfactory result in the context of convergence performance of
TLMS algorithm. But revious researches directly used the CORDIC block output in
their simulation ignoring the internal step-by-step rotations of the CORDIC
processor. This gives rise to a need for verification of the convergence
performance of the TLMS algorithm to investigate if it actually performs
satisfactorily if implemented with step-by-step CORDIC rotation. This research
work has done this job. It focuses on the internal operations of the CORDIC
hardware, implements the Trigonometric LMS (TLMS) and Hyperbolic LMS (HLMS)
algorithms using actual CORDIC rotations. The obtained simulation results are
highly satisfactory and also it shows that convergence behavior of HLMS is much
better than TLMS.Comment: 12 pages, 5 figures, 1 table. Published in IJCNC;
http://airccse.org/journal/cnc/0710ijcnc08.pdf,
http://airccse.org/journal/ijc2010.htm
Speculative Thread Framework for Transient Management and Bumpless Transfer in Reconfigurable Digital Filters
There are many methods developed to mitigate transients induced when abruptly
changing dynamic algorithms such as those found in digital filters or
controllers. These "bumpless transfer" methods have a computational burden to
them and take time to implement, causing a delay in the desired switching time.
This paper develops a method that automatically reconfigures the computational
resources in order to implement a transient management method without any delay
in switching times. The method spawns a speculative thread when it predicts if
a switch in algorithms is imminent so that the calculations are done prior to
the switch being made. The software framework is described and experimental
results are shown for a switching between filters in a filter bank.Comment: 6 pages, 7 figures, to be presented at American Controls Conference
201
Application of LSI to signal detection: The deltic DFPCC
The development of the DELTIC DFPCC serial mode signal processor is discussed. The processor is designed to detect in the presence of background noise a signal coded into the zero crossings of the waveform. The unique features of the DELTIC DFPCC include versatility in handling a variety of signals and relative simplicity in implementation. A theoretical performance model is presented which predicts the expected value of the output signal as a function of the input signal to noise ratio. Experimental results obtained with the prototype system, which was breadboarded with LSI, MSI and SSI components, are given. The device was compared with other LSI schemes for signal processing and it was concluded that the DELTIC DFPCC is simpler and in some cases more versatile than other systems. With established LSI technology, low frequency systems applicable to sonar and similar problems are feasible
Distributed digital signal processors for multi-body structures
Several digital filter designs were investigated which may be used to process sensor data from large space structures and to design digital hardware to implement the distributed signal processing architecture. Several experimental tests articles are available at NASA Langley Research Center to evaluate these designs. A summary of some of the digital filter designs is presented, an evaluation of their characteristics relative to control design is discussed, and candidate hardware microcontroller/microcomputer components are given. Future activities include software evaluation of the digital filter designs and actual hardware inplementation of some of the signal processor algorithms on an experimental testbed at NASA Langley
A VLSI architecture of JPEG2000 encoder
Copyright @ 2004 IEEEThis paper proposes a VLSI architecture of JPEG2000 encoder, which functionally consists of two parts: discrete wavelet transform (DWT) and embedded block coding with optimized truncation (EBCOT). For DWT, a spatial combinative lifting algorithm (SCLA)-based scheme with both 5/3 reversible and 9/7 irreversible filters is adopted to reduce 50% and 42% multiplication computations, respectively, compared with the conventional lifting-based implementation (LBI). For EBCOT, a dynamic memory control (DMC) strategy of Tier-1 encoding is adopted to reduce 60% scale of the on-chip wavelet coefficient storage and a subband parallel-processing method is employed to speed up the EBCOT context formation (CF) process; an architecture of Tier-2 encoding is presented to reduce the scale of on-chip bitstream buffering from full-tile size down to three-code-block size and considerably eliminate the iterations of the rate-distortion (RD) truncation.This work was supported in part by the China National High Technologies Research Program (863) under Grant 2002AA1Z142
Interpolated-DFT-Based Fast and Accurate Amplitude and Phase Estimation for the Control of Power
The quality of energy produced in renewable energy systems has to be at the
high level specified by respective standards and directives. The estimation
accuracy of grid signal parameters is one of the most important factors
affecting this quality. This paper presents a method for a very fast and
accurate amplitude and phase grid signal estimation using the Fast Fourier
Transform procedure and maximum decay sidelobes windows. The most important
features of the method are the elimination of the impact associated with the
conjugate's component on the results and the straightforward implementation.
Moreover, the measurement time is very short - even far less than one period of
the grid signal. The influence of harmonics on the results is reduced by using
a bandpass prefilter. Even using a 40 dB FIR prefilter for the grid signal with
THD = 38%, SNR = 53 dB and a 20-30% slow decay exponential drift the maximum
error of the amplitude estimation is approximately 1% and approximately 0.085
rad of the phase estimation in a real-time DSP system for 512 samples. The
errors are smaller by several orders of magnitude for more accurate prefilters.Comment: in Metrology and Measurement Systems, 201
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