이동통신 기기에 적합한 재구성이 가능한 다중대역 선형 CMOS 전력증폭기에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 2. 권영우.In this Dissertation, a study on multiband reconfigurable linear CMOS power amplifier (PA) is performed. Since a larger number of frequency bands is allocated for 3G/4G mobile communication standards nowadays, handset PAs are required to support the ever-increasing number of frequency bands. With the advent of high-speed wireless data transmission, handset PAs are also demanded to perform linear power amplification under the wide-band signal condition. Even though the CMOS technology has cost and size benefits, however, designing a watt-level linear CMOS PA is a challenging issue due to low breakdown voltage and nonlinear nature of the CMOS device. To resolve the issues above, this study presents two methods suitable for multiband (MB) linear CMOS PA: a reconfigurable MB matching structure and a linearization technique. The proposed MB structure shares a PA core to reduce the cost and size, and contains the power- and frequency-reconfigurable matching networks as well as the output path-selection function. Thus, it can perform the MB operation requiring multiple frequency bands and target output powers. The reconfiguration mechanism is quantitatively analyzed and experimentally demonstrated. The fabricated tri-band reconfigurable 3G UMTS PA using an InGaP/GaAs heterojunction bipolar transistor (HBT) process for practical handset application showed minimal efficiency degradation of less than 2% by multi-banding, compared with a single-band reference PA. For linearization of a CMOS PA, a phase-based linearization technique is presented. Since the PA nonlinearity is determined by the dynamic AM-AM and AM-PM, the two distortions should simultaneously be considered in linearization. Contrary to the previous works which have focused on the correction of AM-AM distortion by providing an envelope-dependent gate-bias, this work proposes an AM-PM linearizer using a varactor and an envelope-reshaping circuit. This linearizer helps the PA recover AM-AM distortion as well. To validate the usefulness of the proposed linearizer, 1.88 GHz and 0.9 GHz stacked-FET PAs using a 0.32-μm silicon-on-insulator (SOI) CMOS process were designed and fabricated. Measurement results showed that the fabricated 1.88 / 0.9 GHz linear CMOS PAs achieved linear efficiencies (meeting –39 dBc W-CDMA ACLR) of higher than 44 / 49%. Furthermore, a single-chain MB linear CMOS PA was implemented based on the proposed MB reconfiguration and linearization techniques. The fabricated MB PA, which has two outputs and covers five popular uplink UMTS/LTE bands (Band 1/2/4/5/8: 824 ~ 1980 MHz), showed minimal efficiency degradation (< 3.3%) compared to the single-band dedicated CMOS PA with W-CDMA efficiencies in excess of 40.7%. Finally, the signal-bandwidth limiting effect of the envelope-based linear CMOS PA is discussed and a solution is proposed. Due to the time delay during envelope-detection and shaping, a timing mismatch between the incoming RF signal and envelope-reshaped signal occurs, thus resulting in no linearization effect under wide-band signal (LTE 20 MHz or more) conditions. To resolve the problem, a group delay circuit with a compact size is employed and thus the linearization effect of the proposed phase-based linearizer is maintained up to 40 MHz LTE bandwidth.Abstract i Contents iii List of Tables vi List of Figures vii 1. Introduction 1 1.1 Motivation 1 1.2 Multiband PA Structure 4 1.3 Linearization of CMOS PA 6 1.4 Dissertation Organization 7 1.5 References 9 2. A Multiband Reconfigurable Power Amplifier for 3G UMTS Handset Applications 10 2.1 Introduction 10 2.2 Operation Principle of the Reconfigurable Output Matching Network 12 2.2.1 Power Reconfigurable Network (PRN) 14 2.2.2 Frequency Reconfigurable Network (FRN) 17 2.2.3 Path Selection Network (PSN) 20 2.2.4 Experimental Validation of the PRN and FRN 24 2.3 Fabrication and Measurement of a MB UMTS Reconfigurable PA 26 2.3.1 Design 26 2.3.2 Measurement 31 2.4 Summary 37 2.5 References 38 3. Linearization of CMOS Power Amplifier and Its Multiband Application 41 3.1 Introduction 41 3.2 Linearization of CMOS PAs: Prior Arts 43 3.3 Harmonic Termination 46 3.3.1 Operation Analysis 47 3.3.2 Experimental Validation 52 3.4 Control of Gate Bias Modulation Effect 54 3.4.1 Analysis 54 3.4.2 Experimental Validation 60 3.5 Proposed Linearization #1: Hybrid Bias 67 3.6 Proposed Linearization #2: Phase Injection 71 3.6.1 Motivation 71 3.6.2 Phase (Capacitance) Injection 72 3.7 Linear CMOS PA Design 75 3.7.1 Baseline PA Design 76 3.7.2 Linearizer Design 78 3.7.3 Fabrication 82 3.8 Measurement Results 83 3.8.1 CW Measurement 83 3.8.2 W-CDMA Measurement 84 3.8.3 LTE Measurement 87 3.9 A Single-Chain MB Reconfigurable Linear PA in SOI CMOS 90 3.9.1 MB Linear CMOS PA: Design 90 3.9.2 MB Linear CMOS PA: Measurement 94 3.10 Summary 99 3.11 References 100 4. Linearization of CMOS Power Amplifier Convering Wideband Signal 105 4.1 Introduction 105 4.2 Bandwidth Limitation of Envelope-Based Linearizers 106 4.2.1 Analysis 106 4.2.2 Delay Correction 110 4.2.3 Feedforward Envelope-Detection Structure with a Delay T/L 114 4.3 Group Delay Circuit 117 4.3.1 Positive GDC versus Negative GDC 117 4.3.2 Left-Handed T/L-Based GDC 119 4.4 Fabrication and Measurement 122 4.4.1 GDC Measurement 123 4.4.2 LTE Measurement 124 4.5 Summary 127 4.6 References 128 5. Conclusions 130 5.1 Research Summary 130 5.2 Future Works 132 Abstract in Korean 133 Publications 135Docto

High-Power Microwave/ Radio-Frequency Components, Circuits, and Subsystems for Next-Generation Wireless Radio Front-Ends

As the wireless communication systems evolve toward the future generation, intelligence will be the main signature/trend, well known as the concepts of cognitive and software-defined radios which offer ultimate data transmission speed, spectrum access, and user capacity. During this evolution, the human society may experience another round of `information revolution\u27. However, one of the major bottlenecks of this promotion lies in hardware realization, since all the aforementioned intelligent systems are required to cover a broad frequency range to support multiple communication bands and dissimilar standards. As the essential part of the hardware, power amplifiers (PAs) capable of operating over a wide bandwidth have been identified as the key enabling technology. This dissertation focuses on novel methodologies for designing and realizing broadband high-power PAs, their integration with high-quality-factor (high-Q) tunable filters, and relevant investigations on the reliabilities of these tunable devices. It can be basically divided into three major parts: 1.Broadband High-Efficiency Power Amplifiers. Obtaining high PA efficiency over a wide bandwidth is very challenging, because of the difficulty of performing broadband multi-harmonic matching. However, high efficiency is the critical feature for high-performance PAs due to the ever-increasing demands for environmental friendliness, energy saving, and longer battery life. In this research, novel design methodologies of broad-band highly efficient PAs are proposed, including the first-ever mode-transferring PA theory, novel matching network topology, and wideband reconfigurable PA architecture. These techniques significantly advance the state-of-the-art in terms of bandwidth and efficiency. 2.Co-Design of PAs and High-Q Tunable Filters. When implementing the intelligent communication systems, the conventional approach based on independent RF design philosophy suffers from many inherent defects, since no global optimization is achieved leading to degraded overall performance. An attractive method to solve these difficulties is to co-design critical modules of the transceiver chain. This dissertation presents the first-ever co-design of PAs and tunable filters, in which the redundant inter-module matching is entirely eliminated, leading to minimized size & cost and maximized overall performance. The saved hardware resources can be further transferred to enhance system functionalities. Moreover, we also demonstrate that co-design of PAs and filters can lead to more functionalities/benefits for the wireless systems, e.g. efficient and linear amplification of dual-carrier (or multi-carrier) signals. 3.High-Power/Non-Linear Study on Tunable Devices. High-power limitation/power handling is an everlasting theme of tunable devices, as it determines the operational life and is the threshold for actual industrial applications. Under high-power operation, the high RF voltage can lead to failures like tuners\u27 mechanical deflections and gas discharge in the small air spacing of the cavity. These two mechanisms are studied independently with their instantaneous and long-term effects on the device performance. In addition, an anti-biased topology of electrostatic RF MEMS varactors and tunable filters is proposed and experimentally validated for reducing the non-linear effect induced by bias-noise. These investigations will enlighten the designers on how to avoid and/or minimize the non-ideal effects, eventually leading to longer life cycle and performance sustainability of the tunable devices

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Bandpass delta-sigma modulators for radio receivers

This thesis concerns discrete-time (DT) bandpass (BP) ΔΣ modulators targeted for intermediate frequency (IF) analog-to-digital (A/D) conversion in radio receivers. The receiver architecture adopted has to be capable of operating with different radio frequencies, channel bandwidths, and modulation techniques. This is necessary in order to achieve an extensive operating area and the possibility of utilizing a local mobile phone standard or a standard suitable for a specific service. The digital IF receiver is a good choice for a multi-mode and multi-band mobile phone receiver, because the signal demodulation and channel filtering are performed in the digital domain. This increases the flexibility of the receiver and relieves the design of the baseband part, but an A/D conversion with high dynamic range and low power dissipation is required. BP ΔΣ modulators are capable of converting a high-frequency narrow band signal and are therefore suitable for signal digitization in an IF receiver. First, the theory of BP ΔΣ modulators is introduced. It has been determined that resonators are the most critical circuit blocks in the implementation of a high performance BP ΔΣ modulator. Different DT resonator topologies are studied and a double-delay (DD) resonator is found to be the best candidate for a high quality resonator. A new DD switched-capacitor (SC) resonator structure has been designed. Furthermore, two evolution versions of the designed SC resonator are presented and their nonidealities are analyzed. The three designed DD SC resonator structures are a main point of the thesis, together with the experimental results. Five different DT BP ΔΣ modulator circuit structures have been implemented and measured. All three of the designed SC resonators are used in the implemented circuits. The experimental work consists of both single-bit and multi-bit structures, as well as both single-loop and cascade architectures. The circuits have been implemented with a 0.35 μm (Bi)CMOS technology and operate with a 3.0 V supply. The measured maximum signal-to-noise-and-distortion ratios (SNDRs) are 78 dB over 270 kHz (GSM), 75 dB over 1.25 MHz (IS-95), 69 dB over 1.762 MHz (DECT), and 48 dB over 3.84 MHz (WCDMA) bandwidths using a 60 MHz IF signal.reviewe

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

RF techniques for IEEE 802.15.4: circuit design and device modelling

The RF circuitry in the physical layer of any wireless communication node is arguably its most important part. The front-end radio is the hardware that enables communication by transmitting and receiving information. Without a robust and high performance front-end, all other higher layers of signal processing and data handling in a wireless network are irrelevant. This thesis investigates the radio circuitry of wireless-networked nodes, and introduces several proposals for improvement. As an emerging market, analysis starts by examining available and ratified network standards suitable for low power applications. After identifying the IEEE 802.15.4 standard (commercially known as ZigBee) as the one of choice, and analysing several front-end architectures on which its transceiver circuitry can be based, an application, the Tyre Pressure Monitoring System (TPMS) is selected to examine the capabilities of the standard and its most suitable architecture in satisfying the application’s requirements. From this compatibility analysis, the most significant shortcomings are identified as interference and power consumption. The work presented in this thesis focuses on the power consumption issues. A comparison of available high frequency transistor technologies concludes Silicon CMOS to be the most appropriate solution for the implementation of low cost and low power ZigBee transceivers. Since the output power requirement of ZigBee is relatively modest, it is possible to consider the design of a single amplifier block which can act as both a Low Noise Amplifier (LNA) in the receiver chain and a Power Amplifier (PA) on the transmitter side. This work shows that by employing a suitable design methodology, a single dual-function amplifier can be realised which meets the required performance specification. In this way, power consumption and chip area can both be reduced, leading to cost savings so vital to the widespread utilisation of the ZigBee standard. Given the importance of device nonlinearity in such a design, a new transistor model based on independent representation of each of the transistor’s nonlinear elements is developed with the aim of quantifying the individual contribution of each of the transistors nonlinear elements, to the total distortion. The methodology to the design of the dual functionality (LNA/PA) amplifier starts by considering various low noise amplifier architectures and comparing them in terms of the trade-off between noise (required for LNA operation) and linearity (important for PA operation), and then examining the behaviour of the selected architecture (the common-source common-gate cascode) at higher than usual input powers. Due to the need to meet the far apart performance requirements of both the LNA and PA, a unique amplifier design methodology is developed The design methodology is based on simultaneous graphical visualisation of the relationship between all relevant performance parameters and corresponding design parameters. A design example is then presented to demonstrate the effectiveness of the methodology and the quality of trade-offs it allows the designer to make. The simulated performance of the final amplifier satisfies both the requirements of ZigBee’s low noise and power amplification. At 2.4GHz, the amplifier is predicted to have 1.6dB Noise Figure (NF), 6dBm Input-referred 3rd-order Intercept Point (IIP3), and 1dB compression point of -3.5dBm. In low power operation, it is predicted to have 10dB gain, consuming only 8mW. At the higher input power of 0dBm, it is predicted to achieve 24% Power-Added Efficiency (PAE) with 8dB gain and 22mW power consumption. Finally, this thesis presents a set of future research proposals based on problems identified throughout its development

Intelligent Circuits and Systems

ICICS-2020 is the third conference initiated by the School of Electronics and Electrical Engineering at Lovely Professional University that explored recent innovations of researchers working for the development of smart and green technologies in the fields of Energy, Electronics, Communications, Computers, and Control. ICICS provides innovators to identify new opportunities for the social and economic benefits of society.　 This conference bridges the gap between academics and R&D institutions, social visionaries, and experts from all strata of society to present their ongoing research activities and foster research relations between them. It provides opportunities for the exchange of new ideas, applications, and experiences in the field of smart technologies and finding global partners for future collaboration. The ICICS-2020 was conducted in two broad categories, Intelligent Circuits & Intelligent Systems and Emerging Technologies in Electrical Engineering