Analysis of Minimal LDPC Decoder System on a Chip Implementation

This paper presents a practical method of potential replacement of several different Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes with one, with the intention of saving as much memory as required to implement the LDPC encoder and decoder in a memory-constrained System on a Chip (SoC). The presented method requires only a very small modification of the existing encoder and decoder, making it suitable for utilization in a Software Defined Radio (SDR) platform. Besides the analysis of the effects of necessary variable-node value fixation during the Belief Propagation (BP) decoding algorithm, practical standard-defined code parameters are scrutinized in order to evaluate the feasibility of the proposed LDPC setup simplification. Finally, the error performance of the modified system structure is evaluated and compared with the original system structure by means of simulation

Error performance prediction of randomly shortened and punctured LDPC codes

In this contribution, we show that the word error rate (WER) performance in the waterfall region of a randomly shortened and punctured low density parity check code can be accurately predicted from the WER performance of its finitelength mother code. We derive an approximate analytical expression for the mutual information (MI) required by a daughter code to achieve a given WER, based on the MI required by the mother code, which shows that the gap to the capacity of the daughter code grows the more the code is punctured or shortened. The theoretical results are confirmed by simulations (where the random shortening and puncturing pattern is either selected independently per codeword or kept the same for all codewords) for practical codes on both the binary erasure channel and the binary-input additive white Gaussian noise channel