7 research outputs found

    Benchmarking, Research, Development, and Support for ORNL Automated Image and Signature Retrieval (AIR/ASR) Technologies

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    Fabrication and nanoroughness characterization of specific nanostructures and nanodevice

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    Nanoroughness is becoming a very important specification for many nanostructures and nanodevices, and its metrology impacts not only the nanodevice properties of interest, but also its material selection and process development. This Ph.D. thesis presents an investigation into fabrication and nanoroughness characterization of nanoscale specimens and MIS (metal-insulator-semiconductor) capacitors with 2 HfO as a high k dielectric. Self-affine curves and Gaussian, non-Gaussian, self-affine as well as complicated rough surfaces were characterized and simulated. The effects of characteristic parameters on the CD (critical dimension) variation and the properties of these rough surfaces were visualized. Compared with experimental investigations, these simulations are flexible, low cost and highly efficient. Relevant conclusions were frequently employed in subsequent investigations. A proposal regarding the thicknesses of the deposited films represented by nominal linewidths and pitch was put forward. The MBE (Molecular Beam Epitaxy) process was introduced and AlGaAs and GaAs were selected to fabricate nanolinewidth and nanopitch specimens on GaAs substrate with nominal linewidths of 2nm, 4nm, 6nm and 8nm, and a nominal pitch of 5nm. HRTEM (High Resolution Transmission Electron Microscopy) image-based characterization of LER/LWR (Line Edge Roughness/Line Width Roughness) in real space and frequency domains demonstrated that the MBE-based process was capable of fabricating the desired nanolinewidth and nanopitch specimens and could be regulated accordingly. MIS capacitors with 2 HfO film as high k dielectric were fabricated, and SEM (Scanning Electron Microscope) image-based nanoroughness characterization, along with measurement of the MIS capacitor electrical properties were performed. It was concluded that the annealing temperature of the deposited 2 HfO film was an important process parameter and 700℃ was an optimal temperature to improve the properties of the MIS capacitor. Also, by quantitative characterization of the relevant nanoroughness, the fabrication process can be further regulated. The uncertainty propagation model of SEM based nanoroughness measurement was presented according to specific requirements of the relevant standards, ISO GPS (Geometric Product Specifications and Verification) and GUM (Guide to the Expression of Uncertainty in Measurement), and the method for implementating uncertainties was evaluated. The case study demonstrated that the total standard uncertainty of the nanoroughness measurement was 0.13nm, while its expanded uncertainty with the coverage factor k as 3 was 0.39nm. They are indispensable parts of LER/LWR measurement results

    Semiconductor Sidewall Shape Estimation

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    We present modifications to a feature-based, image-retrieval approach for estimating semiconductor sidewall (crosssection) shapes using top-down images. The top-down images are acquired by a critical dimension scanning electron microscope (CD-SEM). The proposed system is based upon earlier work with several modifications. First, we use only line-edge, as opposed to full-line, sub-images from the top-down images. Secondly, Gabor filter features are introduced to replace some of the previously computed features. Finally, a new dimensionality reduction algorithm – direct, weighted linear discriminant analysis (DW-LDA) – is developed to replace the previous two-step principal component analysis plus LDA method. Results of the modified system are presented for data collected across several line widths, line spacings, and CD-SEM tools. Keywords: CD-SEM metrology, semiconductor inspection, lithography, linear discriminant analysis (LDA) 1. BACKGROUND In current fabrication environments, line-width measurements in semiconductor lithography are made almost exclusively using scanning electron microscope (SEM) images. This process – known as critical dimension SEM (CD-SEM) metrology – employs images that are usually acquired in a top-down configuration, i.e., looking down onto the semiconductor line feature. According to the International Technology Roadmap for Semiconductors, continually shrinking line-widths mak

    Semiconductor sidewall shape estimation

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    Semiconductor sidewall shape estimation using top-down CD-SEM image retrieval

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