Self-Reconfigurable Analog Arrays: Off-The Shelf Adaptive Electronics for Space Applications

Development of analog electronic solutions for space avionics is expensive and lengthy. Lack of flexible analog devices, counterparts to digital Field Programmable Gate Arrays (FPGA), prevents analog designers from benefits of rapid prototyping. This forces them to expensive and lengthy custom design, fabrication, and qualification of application specific integrated circuits (ASIC). The limitations come from two directions: commercial Field Programmable Analog Arrays (FPAA) have limited variability in the components offered on-chip; and they are only qualified for best case scenarios for military grade (-55C to +125C). In order to avoid huge overheads, there is a growing trend towards avoiding thermal and radiation protection by developing extreme environment electronics, which maintain correct operation while exposed to temperature extremes (-180degC to +125degC). This paper describes a recent FPAA design, the Self-Reconfigurable Analog Array (SRAA) developed at JPL. It overcomes both limitations, offering a variety of analog cells inside the array together with the possibility of self-correction at extreme temperatures

Fiscal year 1979 scientific and technical reports, articles, papers and presentations

This bibliography lists approximately 590 formal NASA technical reports, papers published in technical journals, presentations by MSFC personnel, and reports of MSFC contractors introduced into the NASA scientific and technical information system in 1979

A Review of NASA's Radiation-Hardened Electronics for Space Environments Project

NASA's Radiation Hardened Electronics for Space Exploration (RHESE) project develops the advanced technologies required to produce radiation hardened electronics, processors, and devices in support of the requirements of NASA's Constellation program. Over the past year, multiple advancements have been made within each of the RHESE technology development tasks that will facilitate the success of the Constellation program elements. This paper provides a brief review of these advancements, discusses their application to Constellation projects, and addresses the plans for the coming year

New Design Techniques for Dynamic Reconfigurable Architectures

L'abstract è presente nell'allegato / the abstract is in the attachmen

Fault and Defect Tolerant Computer Architectures: Reliable Computing With Unreliable Devices

This research addresses design of a reliable computer from unreliable device technologies. A system architecture is developed for a fault and defect tolerant (FDT) computer. Trade-offs between different techniques are studied and yield and hardware cost models are developed. Fault and defect tolerant designs are created for the processor and the cache memory. Simulation results for the content-addressable memory (CAM)-based cache show 90% yield with device failure probabilities of 3 x 10(-6), three orders of magnitude better than non fault tolerant caches of the same size. The entire processor achieves 70% yield with device failure probabilities exceeding 10(-6). The required hardware redundancy is approximately 15 times that of a non-fault tolerant design. While larger than current FT designs, this architecture allows the use of devices much more likely to fail than silicon CMOS. As part of model development, an improved model is derived for NAND Multiplexing. The model is the first accurate model for small and medium amounts of redundancy. Previous models are extended to account for dependence between the inputs and produce more accurate results

Choose-Your-Own Adventure: A Lightweight, High-Performance Approach To Defect And Variation Mitigation In Reconfigurable Logic

For field-programmable gate arrays (FPGAs), fine-grained pre-computed alternative configurations, combined with simple test-based selection, produce limited per-chip specialization to counter yield loss, increased delay, and increased energy costs that come from fabrication defects and variation. This lightweight approach achieves much of the benefit of knowledge-based full specialization while reducing to practical, palatable levels the computational, testing, and load-time costs that obstruct the application of the knowledge-based approach. In practice this may more than double the power-limited computational capabilities of dies fabricated with 22nm technologies. Contributions of this work: • Choose-Your-own-Adventure (CYA), a novel, lightweight, scalable methodology to achieve defect and variation mitigation • Implementation of CYA, including preparatory components (generation of diverse alternative paths) and FPGA load-time components • Detailed performance characterization of CYA – Comparison to conventional loading and dynamic frequency and voltage scaling (DFVS) – Limit studies to characterize the quality of the CYA implementation and identify potential areas for further optimizatio

Particle Computation: Complexity, Algorithms, and Logic

We investigate algorithmic control of a large swarm of mobile particles (such as robots, sensors, or building material) that move in a 2D workspace using a global input signal (such as gravity or a magnetic field). We show that a maze of obstacles to the environment can be used to create complex systems. We provide a wide range of results for a wide range of questions. These can be subdivided into external algorithmic problems, in which particle configurations serve as input for computations that are performed elsewhere, and internal logic problems, in which the particle configurations themselves are used for carrying out computations. For external algorithms, we give both negative and positive results. If we are given a set of stationary obstacles, we prove that it is NP-hard to decide whether a given initial configuration of unit-sized particles can be transformed into a desired target configuration. Moreover, we show that finding a control sequence of minimum length is PSPACE-complete. We also work on the inverse problem, providing constructive algorithms to design workspaces that efficiently implement arbitrary permutations between different configurations. For internal logic, we investigate how arbitrary computations can be implemented. We demonstrate how to encode dual-rail logic to build a universal logic gate that concurrently evaluates and, nand, nor, and or operations. Using many of these gates and appropriate interconnects, we can evaluate any logical expression. However, we establish that simulating the full range of complex interactions present in arbitrary digital circuits encounters a fundamental difficulty: a fan-out gate cannot be generated. We resolve this missing component with the help of 2x1 particles, which can create fan-out gates that produce multiple copies of the inputs. Using these gates we provide rules for replicating arbitrary digital circuits.Comment: 27 pages, 19 figures, full version that combines three previous conference article