Transient Safe Operating Area (tsoa) For Esd Applications

A methodology to obtain design guidelines for gate oxide input pin protection and high voltage output pin protection in Electrostatic Discharge (ESD) time frame is developed through measurements and Technology Computer Aided Design (TCAD). A set of parameters based on transient measurements are used to define Transient Safe Operating Area (TSOA). The parameters are then used to assess effectiveness of protection devices for output and input pins. The methodology for input pins includes establishing ESD design targets under Charged Device Model (CDM) type stress in low voltage MOS inputs. The methodology for output pins includes defining ESD design targets under Human Metal Model (HMM) type stress in high voltage Laterally Diffused MOS (LDMOS) outputs. First, the assessment of standalone LDMOS robustness is performed, followed by establishment of protection design guidelines. Secondly, standalone clamp HMM robustness is evaluated and a prediction methodology for HMM type stress is developed based on standardized testing. Finally, LDMOS and protection clamp parallel protection conditions are identifie

The 1st International Conference on Computational Engineering and Intelligent Systems

Computational engineering, artificial intelligence and smart systems constitute a hot multidisciplinary topic contrasting computer science, engineering and applied mathematics that created a variety of fascinating intelligent systems. Computational engineering encloses fundamental engineering and science blended with the advanced knowledge of mathematics, algorithms and computer languages. It is concerned with the modeling and simulation of complex systems and data processing methods. Computing and artificial intelligence lead to smart systems that are advanced machines designed to fulfill certain specifications. This proceedings book is a collection of papers presented at the first International Conference on Computational Engineering and Intelligent Systems (ICCEIS2021), held online in the period December 10-12, 2021. The collection offers a wide scope of engineering topics, including smart grids, intelligent control, artificial intelligence, optimization, microelectronics and telecommunication systems. The contributions included in this book are of high quality, present details concerning the topics in a succinct way, and can be used as excellent reference and support for readers regarding the field of computational engineering, artificial intelligence and smart system

Self-protection capability of integrated NLDMOS power arrays in ESD pulse regimes

This paper provides a review of most recent cycle of studies of NLDMOS-based power arrays, their operation in ESD regimes, self-protection capability as well as the methods and measures to improve the array robustness on the device structure, layout architecture and array composition levels. Effective practices of improving ESD robustness at the cell level and backend level are presented followed by topology optimization. Discussion is based upon ESD characterization supported both by device-circuit mixed-mode and 2.5D array level simulations data. (C) 2011 Elsevier Ltd. All rights reserved

Self-Protection Capability Of Integrated Nldmos Power Arrays In Esd Pulse Regimes

This paper provides a review of most recent cycle of studies of NLDMOS-based power arrays, their operation in ESD regimes, self-protection capability as well as the methods and measures to improve the array robustness on the device structure, layout architecture and array composition levels. Effective practices of improving ESD robustness at the cell level and backend level are presented followed by topology optimization. Discussion is based upon ESD characterization supported both by device-circuit mixed-mode and 2.5D array level simulations data. © 2011 Elsevier Ltd. All rights reserved