Self-Directed Channel Memristor for High Temperature Operation

Ion-conducting memristors comprised of the layered chalcogenide materials Ge2Se3/SnSe/Ag are described. The memristor, termed a self-directed channel (SDC) device, can be classified as a generic memristor and can tolerate continuous high temperature operation (at least 150 °C). Unlike other chalcogenide-based ion conducting device types, the SDC device does not require complicated fabrication steps, such as photodoping or thermal annealing, making these devices faster and more reliable to fabricate. Device pulsed response shows fast state switching in the 10−9 s range. Device cycling at both room temperature and 140 °C show write endurance of at least 1 billion

Comparison of the Electrical Response of Cu and Ag Ion-Conducting SDC Memristors Over the Temperature Range 6 K to 300 K

Electrical performance of self-directed channel (SDC) ion-conducting memristors which use Ag and Cu as the mobile ion source are compared over the temperature range of 6 K to 300 K. The Cu-based SDC memristors operate at temperatures as low as 6 K, whereas Ag-based SDC memristors are damaged if operated below 125 K. It is also observed that Cu reversibly diffuses into the active Ge2Se3 layer during normal device shelf-life, thus changing the state of a Cu-based memristor over time. This was not observed for the Ag-based SDC devices. The response of each device type to sinusoidal excitation is provided and shows that the Cu-based devices exhibit hysteresis lobe collapse at lower frequencies than the Ag-based devices. In addition, the pulsed response of the device types is presented

Ultra-low power logic in memory with commercial grade memristors and FPGA-based smart-IMPLY architecture

Reducing power consumption in nowadays computer technologies represents an increasingly difficult challenge. Conventional computing architectures suffer from the so-called von Neumann bottleneck (VNB), which consists in the continuous need to exchange data and instructions between the memory and the processing unit, leading to significant and apparently unavoidable power consumption. Even the hardware typically employed to run Artificial Intelligence (AI) algorithms, such as Deep Neural Networks (DNN), suffers from this limitation. A change of paradigm is so needed to comply with the ever-increasing demand for ultra-low power, autonomous, and intelligent systems. From this perspective, emerging memristive non-volatile memories are considered a good candidate to lead this technological transition toward the next-generation hardware platforms, enabling the possibility to store and process information in the same place, therefore bypassing the VNB. To evaluate the state of current public-available devices, in this work commercial-grade packaged Self Directed Channel memristors are thoroughly studied to evaluate their performance in the framework of in-memory computing. Specifically, the operating conditions allowing both analog update of the synaptic weight and stable binary switching are identified, along with the associated issues. To this purpose, a dedicated yet prototypical system based on an FPGA control platform is designed and realized. Then, it is exploited to fully characterize the performance in terms of power consumption of an innovative Smart IMPLY (SIMPLY) Logic-in-Memory (LiM) computing framework that allows reliable in-memory computation of classical Boolean operations. The projection of these results to the nanoseconds regime leads to an estimation of the real potential of this computing paradigm. Although not investigated in this work, the presented platform can also be exploited to test memristor-based SNN and Binarized DNNs (i.e., BNN), that can be combined with LiM to provide the heterogeneous flexible architecture envisioned as the long-term goal for ubiquitous and pervasive AI

uMemristorToolbox : Open source framework to control memristors in Unity for ternary applications

Author's accepted manuscript.© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.acceptedVersio

Effective current-driven memory operations for low-power ReRAM applications

© 2023 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Al document ha d’aparèixer l’enllaç a la publicació original a IEEE, o bé al Digital Object Identifier (DOI).Resistive switching (RS) devices are electronic components which exhibit a resistive state that can be adjusted to different nonvolatile levels via electrical stressing, fueling the development of future resistive memories (ReRAM) and enabling innovative solutions for several applications. Most works so far have used voltage-based driving schemes for both WRITE and READ operations. However, results from current-driven WRITE operations have shown high uniformity in switching performance, and thus constitute a valid alternative to consider, but current-driven READ operations have rarely been explored. In this context, here we tested a current-based READ/WRITE memory driving scheme on commercial self-directed channel (SDC) devices, while operating constantly at low current levels between tenths of nA and 1.5 uA. We propose a novel method to carry out efficient READ operations exploiting the transient response of the voltage on the current-driven ReRAM memory cells. For READ operations performed at 100 nA, we calculated the cumulative probability distribution of the standard deviation of the measured voltage ( σV ) on the devices and we observed a ratio σV−HRS/σV−LRS∼10× . Moreover, the HRS and LRS states were distinguishable in all the tested devices with less than 0.5% error. Finally, the calculated energy consumption ( ESET≈10 nJ, ERESET≈30 nJ, and EREAD between 80–400 pJ) was competitive even when the duration of the READ/WRITE current pulses was suboptimal in the millisecond range. Therefore, the presented results validate the promising characteristics and the power-efficiency of the proposed READ method for current-driven ReRAM circuits and applications.This work was supported in part by the Chilean Government through the National Fund for Scientific and Technological Development (FONDECYT) under Grant 1221747; in part by the National Agency for Research and Development (ANID)-Basal under Grant FB0008; in part by the MICINN, Spain, through PRITES Project under Grant PID2019-105658RB-I00; and in part by FLEXRRAM Project under Grant TED2021-129643B-I00.Peer ReviewedPostprint (published version

Memristors for the Curious Outsiders

We present both an overview and a perspective of recent experimental advances and proposed new approaches to performing computation using memristors. A memristor is a 2-terminal passive component with a dynamic resistance depending on an internal parameter. We provide an brief historical introduction, as well as an overview over the physical mechanism that lead to memristive behavior. This review is meant to guide nonpractitioners in the field of memristive circuits and their connection to machine learning and neural computation.Comment: Perpective paper for MDPI Technologies; 43 page

Stochastic resonance exploration in current-driven ReRAM devices

© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Advances in emerging resistive random-access memory (ReRAM) technology show promise for its use in future computing systems, enabling neuromorphic and memory-centric computing architectures. However, one aspect that holds back the widespread practical use of ReRAM is the behavioral variability of resistive switching devices. In this context, a radically new path towards ReRAM-based electronics concerns the exploitation of noise and the Stochastic Resonance (SR) phenomenon as a mechanism to mitigate the impact of variability. While SR has been already demonstrated in ReRAM devices and its potential impact has been analyzed for memory applications, related works have only focused on voltage input signals. In this work we present preliminary results concerning the exploration of SR in current-driven ReRAM devices, commercially available by Knowm Inc. Our results indicate that additive noise of amplitude s = 0.125uA can stabilize the cycling performance of the devices, whereas higher noise amplitude improves the HRS-LRS resistance window, thus could affect positively the Bit Error Rate (BER) metric in ReRAM memory applications.Supported by the Chilean research grants FONDECYT INICIACION 11180706 and ANID-Basal FB0008, and by the Spanish MCIN grants PID2019-105658RB-I00, and MCIN/AEI/10.13039/501100011033 grant PID2019-103869RB-C33.Peer ReviewedPostprint (author's final draft

Exploring the “resistance change per energy unit” as universal performance parameter for resistive switching devices

© Elsevier. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/Resistive switching (RS) device (memristor) technology is continuously maturing towards industrial establishment. There are RS devices that demonstrate an “incremental” (analog) switching behavior, whereas others change their state in a binary form. The final achieved resistance is generally a function of the applied pulse characteristics, i.e. amplitude and duration. However, variability —both from device to device but also from cycle to cycle— and the stochastic nature of internal RS phenomena, still hold back any universal tuning approach based solely on these two magnitudes, making also difficult the qualitative comparison between devices with different material compounds owing to the required SET/RESET voltages being dependent on the biasing conditions. In this work we demonstrate experimentally using commercial RS devices from Knowm Inc. that the switching energy is very insensitive to the biasing conditions. We explored experimentally the SET-RESET behavior of bipolar RS devices from the energy point of view. We figured out the quantitative effect of the injected energy to the resistive state of the devices, and proposed an analytical model to explain our observations in the energy consumed by the device during the switching process. Our results lay the foundations for the definition of “resistance change per energy unit” as a performance parameter for this emerging device technology.Peer ReviewedPostprint (author's final draft

Biologically Plausible Information Propagation in a CMOS Integrate-and-Fire Artificial Neuron Circuit with Memristive Synapses

Neuromorphic circuits based on spikes are currently envisioned as a viable option to achieve brain-like computation capabilities in specific electronic implementations while limiting power dissipation given their ability to mimic energy efficient bio-inspired mechanisms. While several network architectures have been developed to embed in hardware the bio-inspired learning rules found in the biological brain, such as the Spike Timing Dependent Plasticity, it is still unclear if hardware spiking neural network architectures can handle and transfer information akin to biological networks. In this work, we investigate the analogies between an artificial neuron combining memristor synapses and rate-based learning rule with biological neuron response in terms of information propagation from a theoretical perspective. Bio-inspired experiments have been reproduced by linking the biological probability of release with the artificial synapses conductance. Mutual information and surprise have been chosen as metrics to evidence how, for different values of synaptic weights, an artificial neuron allows to develop a reliable and biological resembling neural network in terms of information propagation and analysi