Investigation on solid-phase crystallization techniques for low temperature polysilicon thin-film transistors

Low-temperature polysilicon (LTPS) has emerged as a dominant technology for high performance thin-film transistors (TFTs) used in mobile liquid crystal display (LCD) and organic light emitting diode (OLED) display products. As users demand higher quality in flat panel displays with a larger viewing area and finer resolution, the improvement in carrier mobility of LTPS compared to that of hydrogenated amorphous silicon (a-Si:H) makes it an excellent candidate as a channel material for TFT. Advantages include improvements in switching speed and the ability to incorporate peripheral scan and data driver circuitry onto a low cost display substrate. Solid-phase crystallization (SPC) is a useful technique to realize polysilicon films due to its simplicity and low cost compared to excimer-laser annealing (ELA),which has many challenges in back-plane manufacturing on large glass panels.Metal induced crystallization (MIC) results in polycrystalline silicon films with grain size as large as tens of microns. Flash-lamp annealing (FLA) is a new and novel method to crystallize a-Si films at high temperature without distortion of the glass substrate by performing an annealing within millisecond range.This work investigates SPC, MIC and FLA techniques to realize LTPS films. In addition, TFTs were designed and fabricated to characterize the device quality of the semiconductor layer, and to compare the performance of different structural arrangements

Diamond semiconductor technology for RF device applications

This paper presents a comprehensive review of diamond electronics from the RF perspective. Our aim was to find and present the potential, limitations and current status of diamond semiconductor devices as well as to investigate its suitability for RF device applications. While doing this, we briefly analysed the physics and chemistry of CVD diamond process for a better understanding of the reasons for the technological challenges of diamond material. This leads to Figure of Merit definitions which forms the basis for a technology choice in an RF device/system (such as transceiver or receiver) structure. Based on our literature survey, we concluded that, despite the technological challenges and few mentioned examples, diamond can seriously be considered as a base material for RF electronics, especially RF power circuits, where the important parameters are high speed, high power density, efficient thermal management and low signal loss in high power/frequencies. Simulation and experimental results are highly regarded for the surface acoustic wave (SAW) and field emission (FE) devices which already occupies space in the RF market and are likely to replace their conventional counterparts. Field effect transistors (FETs) are the most promising active devices and extremely high power densities are extracted (up to 30 W/mm). By the surface channel FET approach 81 GHz operation is developed. Bipolar devices are also promising if the deep doping problem can be solved for operation at room temperature. Pressure, thermal, chemical and acceleration sensors have already been demonstrated using micromachining/MEMS approach, but need more experimental results to better exploit thermal, physical/chemical and electronic properties of diamond

Implant Activated Source/Drain Regions for Self-Aligned IGZO TFT

In this work, amorphous Indium Gallium Zinc Oxide (IGZO) TFTs with channel lengths scaled as small as L = 1 µm are presented which demonstrate excellent electrical characteristics, however the traditional metal-contact defined source/drain regions typically require several microns of gate overlap in order to provide ohmic behavior with minimal series resistance and ensure tolerance to overlay error. In addition, further scaling the channel length by simply reducing the source/drain metal gap is not feasible. The focus of this study is to investigate techniques to realize self-aligned (SA) IGZO TFTs that are not subject to gate-source/drain misalignment due to overlay error or process bias. Top gate (TG) co-planar and bottom gate (BG) staggered TFTs are fabricated using plasma immersion and ion implantation to selectively form conductive IGZO regions, with the channel region blocked by a gate-defined mask. Among the investigated treatments, oxygen plasma activation and ion implanted activation via 11B+ and 40Ar+ has been successfully demonstrated. Due to metal gate charging during ion implantation of SA-TG devices, the characteristics show a significant left-shift whereas SA-BG devices do not show this behavior. Electrical results suggest a defect-induced mechanism is involved with 40Ar+ implant activation of the S/D regions. However, 11B+ implant activation is attributed to the formation of an electrically active donor species involving chemical bonding. Both boron and argon demonstrate pronounced degradation in charge injection at higher dose treatments. Finally, a novel lithographic strategy which utilizes top-side flood exposure rather than a back-side through-glass exposure has also been explored, which would enable SA-BG devices on non-transparent substrates

Interpretation and Physical Modeling of Electronic Transport and Defect States in IGZO Thin-Film Transistors

This work is a comprehensive study on the interpretation and modeling of electronic transport behavior and defect states in indium-gallium-zinc-oxide (IGZO) TFTs. Key studies have focused on advancing the state of IGZO TFTs by addressing several challenges in device stability, scaling, and device modeling. These studies have provided new insight on the associated mechanisms and have resulted in the realization of scaled thin-film transistors that exhibit excellent electrical performance and stability. This work has demonstrated the ability to scale the conventional inverted staggered IGZO TFT down to one micron channel length, with excellent on-state and off-state performance where the VT ≈1 V, µeff =12 cm2/Vs, Ileak ≤ 10-12 A/µm and SS ≈ 160 mV/dec. The working source/drain electrodes are direct metal contact regions to the IGZO, which requires several microns of gate overlap to provide ohmic behavior with minimal series resistance and ensure tolerance to overlay error. New results utilizing ion implantation for self-aligned source/drain regions present a path towards submicron channel length. This strategy offers a reduction in channel length as well as parasitic capacitance, which translates to improvement in RC delay and associated voltage losses due to charge-sharing. The realization of self-aligned TFTs using boron ion implantation for selective activation was introduced in a first-time report of boron-doped IGZO. Cryogenic measurements made on long-channel devices has revealed temperature-dependent behavior that is not explained by existing TCAD models employed for defect states and carrier mobility. A completely new device model using Silvaco Atlas has been established which properly accounts for the role of donor-like oxygen vacancy defects, acceptor-like band-tail states, acceptor-like interface traps, and a temperature-dependent intrinsic channel mobility. The developed model demonstrates a remarkable match to transfer characteristics measured at T = 150 K to room temperature. A power-law fit for the µch = f(T) relationship, which resembles 〖μ ~ T〗^((+3)⁄2) behavior consistent with ionized defect scattering. The mobility model is expressly independent of carrier concentration, without dependence on the applied gate bias. The device model is consistent with a compact model developed for circuit simulation (SPICE) that has been recently refined to include on-state and off-state operation. While IGZO is the only AOS technology mature enough for commercialization, the effective electron channel mobility µeff ~ 10 cm2/Vs presents a performance limitation. Other candidate AOS materials which have higher reported channel mobility values have also been investigated; specifically, indium-tungsten-oxide (IWO) and indium-gallium-tin-oxide (ITGO). These investigations serve as preliminary studies; device characteristics support the claims of high channel mobility; however the influence of defect states clearly indicates the need for further process development. The advancements realized in IGZO TFTs in this work will serve as a foundation for these alternative AOS materials

Interpretation and Regulation of Electronic Defects in IGZO TFTs Through Materials & Processes

The recent rise in the market for consumer electronics has fueled extensive research in the field of display. Thin-Film Transistors (TFTs) are used as active matrix switching devices for flat panel displays such as LCD and OLED. The following investigation involves an amorphous metal-oxide semiconductor that has the potential for improved performance over current technology, while maintaining high manufacturability. Indium-Gallium-Zinc-Oxide (IGZO) is a semiconductor material which is at the onset of commercialization. The low-temperature large-area deposition compatibility of IGZO makes it an attractive technology from a manufacturing standpoint, with an electron mobility that is 10 times higher than current amorphous silicon technology. The stability of IGZO TFTs continues to be a challenge due to the presence of defect states and problems associated with interface passivation. The goal of this dissertation is to further the understanding of the role of defect states in IGZO, and investigate materials and processes needed to regulate defects to the level at which the associated influence on device operation is controlled. The relationships between processes associated with IGZO TFT operation including IGZO sputter deposition, annealing conditions and back-channel passivation are established through process experimentation, materials analysis, electrical characterization, and modeling of electronic properties and transistor behavior. Each of these components has been essential in formulating and testing several hypotheses on the mechanisms involved, and directing efforts towards achieving the goal. Key accomplishments and quantified results are summarized as follows: • XPS analysis identified differences in oxygen vacancies in samples before and after oxidizing ambient annealing at 400 °C, showing a drop in relative integrated area of the O 1s peak from 32% to 19%, which experimentally translates to over a thousand fold decrease in the channel free electron concentration. • Transport behavior at cryogenic temperatures identified variable range hopping as the electron transport mechanism at temperature below 130 K, whereas at temperature greater than 130 K, the current vs temperature response followed an Arrhenius relationship consistent with extended state transport. • Refinement of an IGZO material model for TCAD simulation, which consists of oxygen vacancy donors providing an integrated space charge concentration NVO = +5e15 cm-3, and acceptor-like band-tail states with a total integrated ionized concentration of NTA = -2e18 cm-3. An intrinsic electron mobility was established to be Un = 12.7 cm2/V∙s. • A SPICE-compatible 2D on-state operation model for IGZO TFTs has been developed which includes the integration of drain-impressed deionization of band-tail states and results in a 2D modification of free channel charge. The model provides an exceptional match to measured data and TCAD simulation, with model parameters for channel mobility (Uch = 12 cm2/V∙s) and threshold voltage (VT = 0.14 V) having a close match to TCAD analogs. • TCAD material and device models for bottom-gate and double-gate TFT configurations have been developed which depict the role of defect states on device operation, as well as provide insight and support of a presented hypothesis on DIBL like device behavior associated with back-channel interface trap inhomogeneity. This phenomenon has been named Trap Associated Barrier Lowering (TABL). • A process integration scheme has been developed that includes IGZO back-channel passivation with PECVD SiO2, furnace annealing in O2 at 400 °C, and a thin capping layer of alumina deposited via atomic layer deposition. This process supports device stability when subjected to negative and positive bias stress conditions, and thermal stability up to 140 °C. It also enables TFT operation at short channel lengths (Leff ~ 3 µm) with steep subthreshold characteristics (SS ~ 120 mV/dec). The details of these contributions in the interpretation and regulation of electronic defect states in IGZO TFTs is presented, along with the support of device characteristics that are among the best reported in the literature. Additional material on a complementary technology which utilizes flash-lamp annealing of amorphous silicon will also be described. Flash-Lamp Annealed Polycrystalline Silicon (FLAPS) has realized n-channel and p-channel TFTs with promising results, and may provide an option for future applications with the highest performance demands. IGZO is rapidly emerging as the candidate to replace a-Si:H and address the performance needs of display products produced by large panel manufacturing

Thin-film transistors fabricated using sputter deposition of zno

Development of thin film transistors (TFTs) with conventional channel layer materials, such as amorphous silicon (a-Si) and polysilicon (poly-Si), has been extensively investigated. A-Si TFT currently serves the large flat panel industry; however advanced display products are demanding better TFT performance because of the associated low electron mobility of a-Si. This has motivated interest in semiconducting metal oxides, such as Zinc Oxide (ZnO), for TFT backplanes. This work involves the fabrication and characterization of TFTs using ZnO deposited by sputtering. An overview of the process details and results from recently fabricated TFTs following a full-factorial designed experiment will be presented. Material characterization and analysis of electrical results will be described. The investigated process variables were the gate dielectric and ZnO sputtering process parameters including power density and oxygen partial pressure. Electrical results showed clear differences in treatment combinations, with certain I-V characteristics demonstrating superior performance to preliminary work. A study of device stability will also be discussed

금속유도 측면결정화 박막 트랜지스터의 전기적 성능 향상을 위한 고귀한 방법

학위논문 (박사)-- 서울대학교 대학원 : 공과대학 재료공학부, 2018. 2. 주승기.금속유도 결정화에 의해 제작된 저온 다결정 실리콘 박막 트랜지스터는 액티브 매트릭스 평판 디스플레이에 사용하기에 매력적이다. 그러나, 금속유도 결정화에 의해 제작된 실리콘 박막의 결정 입계에는 니켈 실리사이드가 존재하며, 이러한 니켈 실리사이드는 큰 누설 전류를 유발한다. 본 연구에서는 게터층으로 비정질 실리콘, 에치 스톱층으로 실리콘 산화막을 사용하여 니켈 불순물을 제거하는 게터링 방법을 이용하여 금속유도 결정화 다결정 실리콘 박막 트랜지스터의 누설 전류를 감소시켰다. 금속유도 결정화 다결정 실리콘 박막의 니켈 트랩 상태 밀도가 게터링에 의해 감소하였으며, 그 결과 금속유도 결정화 다결정 실리콘 박막 트랜지스터의 누설 전류가 감소하였다. 또한, 게터링 횟수가 증가 할수록 금속유도 결정화 다결정 실리콘 박막 트랜지스터의 누설 전류가 점차적으로 감소 하였다. 이러한 게터링에 의한 누설전류 감소 효과를 설명하기 위해 적절한 모델을 제시하였다. 또한 게터링을 니켈 실리사이드 유도 측면결정화 다결정 실리콘 박막 트랜지스터에 적용하여 누설 전류를 더욱 감소 시켰다. 금속유도 측면결정화에 의해 제작된 다결정 실리콘 박막 트랜지스터는 대규모 액티브 매트릭스 평판 디스플레이의 스위칭 및 구동 소자로서 매력적인 장치 중 하나이다. 하지만 금속유도 측면결정화에 의해 제작된 다결정 실리콘 박막 트랜지스터는 누설전류가 크다는 단점을 가지고 있다. 금속유도 측면결정화 다결정 실리콘 박막 트랜지스터의 누설 전류는 게이트 절연체와 다결정 실리콘 활성층 사이의 계면에서 니켈 불순물에 기인한 하전된 트랩 상태에 의해 유도되고, 트랩 상태는 게이트와 드레인 사이의 높은 전계에 의해 활성화된다. 본 연구에서는 2중 노광 방법으로 드레인 오프셋 영역을 형성하여 금속유도 측면결정화 다결정 실리콘 박막 트랜지스터의 누설전류를 감소시켰다. 본 연구에서는 boron 이 금속유도 측면결정화 성장 속도에 미치는 영향을 토대로, boron이 비정질 실리콘의 결정화에 미치는 영향에 대하여 연구하였다. 저압 화학 기상 증착법 및 플라즈마 강화 화학 기상 증착법으로 증착된 비정질 실리콘은 boron에 의한 결정화에 있어 상이한 결과를 보였다. 저압 화학 기상 증착법으로 증착된 비정질 실리콘에 boron 을 도핑 하였을 경우, 니켈을 증착하지 않아도 560℃에서 2시간 내에 실리콘이 결정화 되었지만 플라즈마 강화 화학 기상 증착법으로 증착된 비정질 실리콘은 boron 이 도핑 되어도 니켈 없이는 결정화가 되지 않았다. 하지만 플라즈마 강화 화학 기상 증착법으로 증착된 비정질 실리콘에 boron 을 도핑 할 경우 금속유도 측면결정화 성장 속도가 상당히 증가하였다. 수소 분위기에서 열처리 할 경우 금속유도 측면결정화 성장 속도가 감소하였으며, boron 에 의해 결정화된 실리콘의 면저항이 증가 하였다. 본 연구에서는 이러한 원인을 규명하기 위해 boron 에 의한 실리콘 결정화의 적절한 모델을 제시하였다. 일반 유리기판과 열처리된 유리기판 위에 금속유도 측면결정화 다결정 실리콘 박막 트랜지스터를 제작하여 압축응력이 금속유도 측면결정화 성장 속도 및 전기적 특성에 미치는 영향을 연구하였다. 유리기판의 수축을 억제하기 위해 사전에 550℃에서 40시간동안 유리기판을 열처리하였다. 결정화 및 전기적 활성화 후 일반 유리기판의 변형률은 0.0067% 이었고 열처리된 유리기판의 변형률은 0.0012% 이었다. 일반 유리기판 위에서의 금속유도 측면결정화 성장 속도는 열처리된 유리기판 위에서의 금속유도 측면결정화 성장 속도 보다 느렸다. 유리기판의 수축으로 인한 압축변형은 다결정 실리콘 박막에 마이크로 크랙 및 공극을 증가 시킨 것으로 생각 되며, 그 결과 일반 유리기판 위에 제작된 다결정 실리콘 박막 트랜지스터 의 field effect mobility, threshold voltage, subthreshold slope 이 악화 된 것으로 볼 수 있다. 그리고 일반 유리기판 위에 제작된 다결정 실리콘 박막 트랜지스터는 소자 위치에 따른 불균일한 전기적 특성을 보였다. 반면에, 열처리된 유리기판 위에 제작된 다결정 실리콘 박막 트랜지스터는 뛰어난 전기적 특성과 소자 위치에 따른 균일한 전기적 특성을 보였다.Low-temperature polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) fabricated via metal-induced crystallization (MIC) are attractive candidates for use in active-matrix flat-panel displays. However, these exhibit a large leakage current due to the nickel silicide being trapped at the grain boundaries of the poly-Si. We reduced the leakage current of the MIC poly-Si TFTs by developing a gettering method to remove the Ni impurities using a Si getter layer and natively-formed SiO2 as the etch stop interlayer. The Ni trap state density (Nt) in the MIC poly-Si film decreased after the nickel silicide gettering, and as a result, the leakage current of the MIC poly-Si TFTs decreased. Furthermore, the leakage current of MIC poly-Si TFTs gradually decreased with additional gettering. To explain the gettering effect on MIC poly-Si TFTs, we suggest an appropriate model. Gettering method was also applied to nickel silicide seed induced lateral crystallized (SILC) poly-Si TFTs. Although the nickel silicide was already reduced by SILC, the nickel silicide in the SILC poly-Si film could be further reduced through gettering. As a result, the leakage current of the SILC poly-Si TFTs decreased. Poly-Si TFT fabricated by metal-induced lateral crystallization (MILC) is an attractive candidate for switching and driving elements in large-scaled active-matrix flat-panel displays. However, the MILC poly-Si TFTs have a large leakage current. The leakage current of MILC poly-Si TFTs is induced by charged trap state which is originated from Ni impurities at the interface between gate insulator and poly-Si active layer, and the trap state is activated by high electric field between the gate and the drain. In this study, we developed a double exposure method to form drain offset region. The leakage current of MILC poly-Si TFTs fabricated by double exposure method drastically decreased. In this study, based on the effect of boron on MILC growth rate, we investigated the effects of boron on the crystallization of amorphous silicon (a-Si). Low pressure chemical vapor deposition (LPCVD) a-Si and plasma enhanced chemical vapor deposition (PECVD) a-Si showed different tendencies in crystallization by boron. When LPCVD intrinsic a-Si was doped with boron, a-Si was crystallized without Ni at 560 °C within 2 h, whereas boron-doped PECVD a-Si was not crystallized without Ni. However, the MILC growth rate of boron-doped PECVD a-Si significantly increased. The MILC growth was suppressed when annealed in hydrogen ambient, and the sheet resistance of boron-induced crystallized Si annealed in hydrogen ambient was higher than that annealed in vacuum. To elucidate these phenomena, we suggested an appropriate model of boron-induced silicon crystallization. MILC poly-Si TFTs were fabricated on the compacted glass and the bare glass substrate, and we investigated compressive stress effects on MILC growth rate and electrical properties of MILC poly-Si TFTs. We compacted the glass at 550 °C for 40 h to suppress glass substrate shrinkage. The strain rate of the bare glass substrate was 0.0067% and that of the compacted glass substrate was 0.0012% after crystallization and electrical activation. The MILC growth rate on the bare glass substrate was lower than that on the compacted glass substrate. Compressive strain resulting from glass substrate shrinkage generally increases the size of the micro-cracks and vacancies in Si film, and as a result, field effect mobility, threshold voltage and subthreshold slope of the MILC poly-Si TFTs fabricated on the bare glass substrate deteriorated. The uniformity of electrical properties of MILC poly-Si TFTs was degraded on the bare glass substrate. On the other hand, the MILC poly-Si TFTs fabricated on the compacted glass substrate showed excellent uniformity of electrical properties.Chapter 1. Introduction 1 1.1 Thin-Film Transistors 1 1.2 Flat Panel Displays 2 1.2.1 Liquid Crystal Display 2 1.2.2 Active Matrix Organic Light Emitting Diode 4 Chapter 2. Background and Motivation 5 2.1 Low Temperature Polycrystalline Silicon Thin-Film Transistors 5 2.2 Metal Induced Lateral Crystallization 7 2.3 Electrical Properties of Polycrystalline Silicon Thin-Film Transistors 11 2.3.1 Field-Effect Mobility 11 2.3.2 Threshold Voltage 12 2.3.3 Subthreshold Slope 13 2.3.4 Leakage Current 14 Chapter 3. Gettering 16 3.1 Introduction 16 3.2 Experiment 18 3.3 Result and Discussion 20 3.4 Conclusion 36 Chapter 4. Drain Offset Gate 37 4.1 Introduction 37 4.2 Experiment 39 4.3 Result and Discussion 41 4.4 Conclusion 49 Chapter 5. Boron Induced Low Temperature Polycrystalline Silicon 50 5.1 Introduction 50 5.2 Experiment 52 5.3 Result and Discussion 53 5.4 Conclusion 63 Chapter 6. Polycrystalline Silicon Thin-Film Transistors on Bare Glass Substrate 64 6.1 Introduction 64 6.2 Experiment 66 6.3 Result and Discussion 68 6.4 Conclusion 80 Chapter 7. Conclusion 81 Bibliography 84 Abstract (in Korean) 108 Achievement 112Docto

An indole trimer: synthesis, self-assembly and applications

The organic semiconductor, the indole -5- carboxylic acid asymmetric trimer (ICAT), was chemically synthesised using a new procedure. Self- assembly of ICAT in solution, produced narrowly dispersed discotic nanoparticles that are stable in solution and transferable between surfaces. Highly ordered ICAT bulk molecular and nanoparticle thin films were produced through controlled assembly of ICAT at the solution /solid interface, using glass substrates functionalised with a variety of self assembled monolayers (SAMs). Two films, in particular, on the hydroxyl and the amine -functionalised substrates had extremely well ordered microstructures, suitable for device application.An immersion based deposition technique was developed, where gold and SAM - functionalised glass substrates were immersed in ICAT solutions made with solvents with a range of polarities. At short immersion times, bulk or particulate films were deposited, as a function of immersion solvent. Longer immersion times produced size tailored vertically aligned nanorod and nanowire arrays, as a function of immersion solvent. The immersion time also controlled both the rod density and rod orientation on the substrates. The results were interpreted in terms of heterogeneous nucleation and subsequent growth. Solvophobic forces induced homogeneous nucleation rather than heterogeneous nucleation, in the immersion systems with water and hydrocarbon based immersion solvents. Aligned nanorods and nanowires were assembled on gold and hydroxyl -functionalised glass substrates when polar aprotic immersion solvents were used. There was no obvious correlation between nanostructure dimensions and solvent polarity in these experiments. This is the first time vertically aligned nanorod arrays have been fabricated with small organic functional molecules, through a solution based technique (non -template).Solution based deposition techniques developed here were used to deposit ICAT onto field effect transistors (FETs), resulting in devices with a range of ICAT film morphologies. Single crystal devices were also produced where the ICAT crystal bridged the active channel, defined as the gap between the source and drain electrodes. Several chips, with over 20 FETs on each chip, with each ICAT film morphology type, were fabricated. Selected chips had consistent, reproducible current/voltage (IV) outputs that varied within « one order of magnitude, when probed on all areas. The devices produced n and p -type unipolar activity and the onset of ambipolar activity in ambient conditions, at low voltage probing ranges. Carrier type was dependent on the film morphology. Device lifetime was dependent on film thickness

High-throughput large-area plastic nanoelectronics

Large-area electronics (LAE) manufacturing has been a key focus of both academic and industrial research, especially within the last decade. The growing interest is born out of the possibility of adding attractive properties (flexibility, light weight or minimal thickness) at low cost to well-established technologies, such as photovoltaics, displays, sensors or enabling the realisation of emerging technologies such as wearable devices and the Internet of Things. As such there has been great progress in the development of materials specifically designed to be employed in solution processed (plastic) electronics, including organic, transparent metal oxide and nanoscale semiconductors, as well as progress in the deposition methods of these materials using low-cost high-throughput printing techniques, such as gravure printing, inkjet printing, and roll-to-roll vacuum deposition. Meanwhile, industry innovation driven by Moore’s law has pushed conventional silicon-based electronic components to the nanoscale. The processes developed for LAE must strive to reach these dimensions. Given that the complex and expensive patterning techniques employed by the semiconductor industry so far are not compatible with LAE, there is clearly a need to develop large-area high throughput nanofabrication techniques. This thesis presents progress in adhesion lithography (a-Lith), a nanogap electrode fabrication process that can be applied over large areas on arbitrary substrates. A-Lith is a self-alignment process based on the alteration of surface energies of a starting metal electrode which allows the removal of any overlap of a secondary metal electrode. Importantly, it is an inexpensive, scalable and high throughput technique, and, especially if combined with low temperature deposition of the active material, it is fundamentally compatible with large-area fabrication of nanoscale electronic devices on flexible (plastic) substrates. Herein, I present routes towards process optimisation with a focus on gap size reduction and yield maximisation. Asymmetric gaps with sizes below 10 nm and yields of > 90 % for hundreds of electrode pairs generated on a single substrate are demonstrated. These large width electrode nanogaps represent the highest aspect ratio nanogaps (up to 108) fabricated to date. As a next step, arrays of Schottky nanodiodes are fabricated by deposition of a suitable semiconductor from solution into the nanogap structures. Of principal interest is the wide bandgap transparent semiconductor, zinc oxide (ZnO). Lateral ZnO Schottky diodes show outstanding characteristics, with on-off ratios of up to 106 and forward current values up to 10 mA for obtained upon combining a-Lith with low-temperature solution processing. These unique devices are further investigated for application in rectifier circuits, and in particular for potential use in radio frequency identification (RFID) tag technology. The ZnO diodes are found to surpass the 13.56 MHz frequency bernchmark used in commercial applications and approach the ultra-high frequency (UHF) band (hundreds of megahertz), outperforming current state of the art printed diodes. Solution processed fullerene (C60) is also shown to approach the UHF band in this co-planar device configuration, highlighting the viability of a-Lith for enabling large-area flexible radio frequency nanoelectronics. Finally, resistive switching memory device arrays based on a-Lith patterned nanogap aluminium symmetric electrodes are demonstrated for the first time. These devices are based either on empty aluminium nanogap electrodes, or with the gap filled with a solution-processed semiconductor, the latter being ZnO, the semiconducting polymer poly(9,9-dioctylfluorene-alt-benzothiadiazole) (F8BT) or carbon nanotube/polyfluorene blends. The switching mechanism, retention time and switching speed are investigated and compared with published data. The fabrication of arrays of these devices illustrates the potential of a-Lith as a simple technique for the realisation of large-area high-density memory applications.Open Acces