Selective Harmonic Mitigation Technique for Cascaded H-Bridge Converters With Nonequal DC Link Voltages

Multilevel converters have received increased interest recently as a result of their ability to generate high quality output waveforms with a low switching frequency. This makes them very attractive for high power applications. A Cascaded HBridge converter is a multilevel topology which is formed from the series connection of H-Bridge cells. Optimized pulse width modulation techniques such as Selective Harmonic Elimination (SHE-PWM) or Selective Harmonic Mitigation (SHM-PWM) are capable of pre-programming the harmonic profile of the output waveform over a range of modulation indices. Such modulation methods may however not perform optimally if the DC links of the Cascaded H-Bridge Converter are not balanced. This paper presents a new SHM-PWM control strategy which is capable of meeting grid codes even under non-equal DC link voltages. The method is based on the interpolation of different sets of angles obtained for specific situations of imbalance. Both simulation and experimental results are presented to validate the proposed control method

Effect of duty cycle on THD for multilevel inverter based on selective harmonic elimination technique

Multilevel inverters controlled suffers from the issue of harmonic distortion in the output voltage. Selective Harmonic Elimination (SHE) technique plays an effective role to eliminate these harmonics. The undesirable odd harmonics can be eliminated by having optimized the switching angles in SHE signal. To optimized and obtained these switching angles, a number of nonlinear equations should be solved using a numerical method. In addition to the modulation index, by changing the value of the duty cycle the Total Harmonics Distortion (THD) will also change. In this paper, a novel Optimization Harmonic Elimination Technique (OHET) based on SHE scheme is proposed in order to minimize Total Harmonic Distortion (THD). To evaluate and investigate the performance of the proposed scheme, a seven-level cascaded inverter is simulated by MATLAB and PSIM software

New grid-tied cascaded multilevel inverter topology with reduced number of switches

Performance of multilevel inverters (MLI) are distinguished because of their low harmonic waveform generation, low filtering requirements on AC side and high voltage application. Among different (MLI) topologies, cascaded multi-level inverters (CMLI) are easier to implement and are much more cost effective. The main drawback of multilevel inverters is requirement of more than one isolated DC source and a lot of switches which makes them bulky and expensive to implement. To address this issue, researchers have investigated new topologies with reduced number of switches compared to conventional multilevel converters. In this paper, a new grid-tied cascaded multi-level topology with reduced number of switches is proposed. Compared to a standard 11-level MLI, the number of switches are reduced. The objective of the design is to reduce the number of DC sources and switches in order to reach the same level of the output voltage. Finally, performance of the proposed topology with a range of modulation and load power factor, operation regarding connection to the grid with closed loop control and comparative study with the other topologies is presented

Delay-Independent Stability Analysis of Linear Time-Delay Systems Based on Frequency

This paper studies strong delay-independent stability of linear time-invariant systems. It is known that delay-independent stability of time-delay systems is equivalent to some frequency-dependent linear matrix inequalities. To reduce or eliminate conservatism of stability criteria, the frequency domain is discretized into several sub-intervals, and piecewise constant Lyapunov matrices are employed to analyze the frequency-dependent stability condition. Applying the generalized Kalman–Yakubovich–Popov lemma, new necessary and sufficient criteria are then obtained for strong delay-independent stability of systems with a single delay. The effectiveness of the proposed method is illustrated by a numerical example