Comparative Analysis Spread Spectrum and Parity Coding Steganography in E-commerce

The transaction data online has increased compared to the previous communications that mostly in the form of voice and text messaging. To improve the security, data must be protected such a way that it cannot be attacked by unauthorized parties. In this case, a good security system must be able to transmit the original information to the second party without having to know the existence and validity by a third party. One of the security systems that can be used is steganography. In this paper, we will compare the performance of Spread Spectrum and Parity Coding in e-commerce based on Android in case of processing time between insertion and retrieval information, and the changing image size during the insertion process. Our experimental results show that parity coding has better performance on client side that use low performance smart phone based on Android operating system and spread spectrum has better performance on blackberry store server that use laptop PC

A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL

Split manufacturing was introduced as an effective countermeasure against hardware-level threats such as IP piracy, overbuilding, and insertion of hardware Trojans. Nevertheless, the security promise of split manufacturing has been challenged by various attacks, which exploit the well-known working principles of physical design tools to infer the missing BEOL interconnects. In this work, we advocate a new paradigm to enhance the security for split manufacturing. Based on Kerckhoff's principle, we protect the FEOL layout in a formal and secure manner, by embedding keys. These keys are purposefully implemented and routed through the BEOL in such a way that they become indecipherable to the state-of-the-art FEOL-centric attacks. We provide our secure physical design flow to the community. We also define the security of split manufacturing formally and provide the associated proofs. At the same time, our technique is competitive with current schemes in terms of layout overhead, especially for practical, large-scale designs (ITC'99 benchmarks).Comment: DATE 2019 (https://www.date-conference.com/conference/session/4.5

RSA ENCRYPTION ALGORITHM AUGUMENTED WITH BIT-STUFFING TECHNIQUE FOR DATA SECURITY

Data transmission through the internet applications is growing very fast, and this continuous growth demands for new network bandwidth and data security. Encryption plays a major role in security of information systems and internet based applications. In this study, the RSA algorithm was modified with bit-stuffing technique to improve the protection and security of confidential data while in transits or in storage. Our modified algorithm, RSA Bit-stuffed, was implemented and compared with the modified Ron Divest Code4 and the modified RSA in MATLAB using time complexity and avalanche effect as performance metrics. The experimental results showed that our augmented bit-insertion technique increased the time complexity against different attacks, boost the randomness of encrypted messages, and also improve security of encryption keys with bit-length lower than that of the standard RSA. &nbsp

SALSy: Security-Aware Layout Synthesis

Integrated Circuits (ICs) are the target of diverse attacks during their lifetime. Fabrication-time attacks, such as the insertion of Hardware Trojans, can give an adversary access to privileged data and/or the means to corrupt the IC's internal computation. Post-fabrication attacks, where the end-user takes a malicious role, also attempt to obtain privileged information through means such as fault injection and probing. Taking these threats into account and at the same time, this paper proposes a methodology for Security-Aware Layout Synthesis (SALSy), such that ICs can be designed with security in mind in the same manner as power-performance-area (PPA) metrics are considered today, a concept known as security closure. Furthermore, the trade-offs between PPA and security are considered and a chip is fabricated in a 65nm CMOS commercial technology for validation purposes - a feature not seen in previous research on security closure. Measurements on the fabricated ICs indicate that SALSy promotes a modest increase in power in order to achieve significantly improved security metrics

PERFORMANCE ANALYSIS OF WATERMARKING APPROACH FOR VLSI DESIGN INTELLECTUAL PROPERTY PROTECTION

VLSI technology brought revolution in EDA industry. Fabrication of complicated system on a chip is possible by using reusable module called Intellectual Property (IP) core. IP cores that became an integral part of the electronic design industry influenced and had a rather significant and almost incomparable impact with respect to system designing in any chip. IP designs for any organization are imperative; contrary, IP designs that are shared can significantly cause high security risks. The majority of IP’s require time as well as effort for purposes of designing and verification, however there still remains the possibility of these being copied or minor modifications to hide proof of ownership. To overcome this problem watermarking technique is recommended for IP Core protection. Watermark insertion in multilevel increases the security of the system. In this paper the ownership information is inserted in state transition outputs of State Transition Graph employing hierarchical representation of Finite state Machine (FSM) and subsequently in the netlist level by embedding watermark in the delay between the states. Watermark insertion at two levels increases the security of the design. Signature generation uses cryptographic algorithm for enhancing the security of the IP core designs. The experimental results show that performance is improved

Adaptive just-in-time code diversification

We present a method to regenerate diversified code dynamically in a Java bytecode JIT compiler, and to update the diversification frequently during the execution of the program. This way, we can significantly reduce the time frame in which attackers can let a program leak useful address space information and subsequently use the leaked information in memory exploits. A proof of concept implementation is evaluated, showing that even though code is recompiled frequently, we can achieved smaller overheads than the previous state of the art, which generated diversity only once during the whole execution of a program

DoS protection for a Pragmatic Multiservice Network Based on Programmable Networks

Proceedings of First International IFIP TC6 Conference, AN 2006, Paris, France, September 27-29, 2006.We propose a scenario of a multiservice network, based on pragmatic ideas of programmable networks. Active routers are capable of processing both active and legacy packets. This scenario is vulnerable to a Denial of Service attack, which consists in inserting false legacy packets into active routers. We propose a mechanism for detecting the injection of fake legacy packets into active routers. This mechanism consists in exchanging accounting information on the traffic between neighboring active routers. The exchange of accounting information must be carried out in a secure way using secure active packets. The proposed mechanism is sensitive to the loss of packets. To deal with this problem some improvements in the mechanism has been proposed. An important issue is the procedure for discharging packets when an attack has been detected. We propose an easy and efficient mechanism that would be improved in future work.Publicad