Scheduling of Batch Processors in Semiconductor Manufacturing – A Review

In this paper a review on scheduling of batch processors (SBP) in semiconductor manufacturing (SM) is presented. It classifies SBP in SM into 12 groups. The suggested classification scheme organizes the SBP in SM literature, summarizes the current research results for different problem types. The classification results are presented based on various distributions and various methodologies applied for SBP in SM are briefly highlighted. A comprehensive list of references is presented. It is hoped that, this review will provide a source for other researchers/readers interested in SBP in SM research and help simulate further interest.Singapore-MIT Alliance (SMA

Performance of a Serial-Batch Processor System with Incompatible Job Families under Simple Control Policies

A typical example of a batch processor is the diffusion furnace used in wafer fabrication facilities (otherwise known as wafer fabs). In diffusion, silicon wafers are placed inside the furnace, and dopant is flown through the wafers via nitrogen gas. The higher the temperature, the faster the dopant penetrates the wafer surface. Then, a thin layer of silicon dioxide is grown, to help the dopant diffuse into the silicon. This operation can take 10 hours or more to finish processing, as compared to one or two hours for other wafer fab operations, according to Uzsoy [8]. Diffusion furnaces typically can process six to eight lots concurrently; we call the lots processed concurrently a batch. The quantity of lots loaded into the furnace does not affect the processing time. Only lots that require the same chemical recipe and temperature may be batched together at the diffusion furnace. We wish to control the production of a manufacturing system, comprised of a serial processor feeding the batch processor. The system produces different job types, and each job can only be batched together with jobs of the same type. More specifically, we explore the idea of controlling the production of the serial processor, based on the wip found in front of the batch processor. We evaluate the performance of our manufacturing system under several simple control policies under a range of loading conditions and determine which control policies perform better under which conditions. It is hoped that the results obtained from this small system could be extended to larger systems involving a batch processor, with particular emphasis placed on the applicability of such policies in wafer fabrication.Singapore-MIT Alliance (SMA

Simulation-Based Analysis on Operational Control of Batch Processors in Wafer Fabrication

[EN] In semiconductor wafer fabrication (wafer fab), wafers go through hundreds of process steps on a variety of processing machines for electrical circuit building operations. One of the special features in the wafer fabs is that there exist batch processors (BPs) where several wafer lots are processed at the same time as a batch. The batch processors have a significant influence on system performance because the repetitive batching and de-batching activities in a reentrant product flow system lead to non-smooth product flows with high variability. Existing research on the BP control problems has mostly focused on the local performance, such as waiting time at the BP stations. This paper attempts to examine how much BP control policies affect the system-wide behavior of the wafer fabs. A simulation model is constructed with which experiments are performed to analyze the performance of BP control rules under various production environments. Some meaningful insights on BP control decisions are identified through simulation results.This work was supported by the Pukyong National University Research Abroad Fund (C-D-2016-0843).Koo, P.; Ruiz García, R. (2020). Simulation-Based Analysis on Operational Control of Batch Processors in Wafer Fabrication. Applied Sciences. 10(17):1-17. https://doi.org/10.3390/app10175936S1171017Wang, L.-C., Chu, P.-C., & Lin, S.-Y. (2019). Impact of capacity fluctuation on throughput performance for semiconductor wafer fabrication. Robotics and Computer-Integrated Manufacturing, 55, 208-216. doi:10.1016/j.rcim.2018.03.005Ham, M. (2012). Integer programming-based real-time dispatching (i-RTD) heuristic for wet-etch station at wafer fabrication. International Journal of Production Research, 50(10), 2809-2822. doi:10.1080/00207543.2011.594816Mathirajan, M., & Sivakumar, A. I. (2006). A literature review, classification and simple meta-analysis on scheduling of batch processors in semiconductor. The International Journal of Advanced Manufacturing Technology, 29(9-10), 990-1001. doi:10.1007/s00170-005-2585-1FOWLER, J. W., HOGG, G. L., & PHILLIPS, D. T. (2000). Control of multiproduct bulk server diffusion/oxidation processes. Part 2: multiple servers. IIE Transactions, 32(2), 167-176. doi:10.1080/07408170008963889Van Der Zee, D. J. (2002). Adaptive scheduling of batch servers in flow shops. International Journal of Production Research, 40(12), 2811-2833. doi:10.1080/00207540210136559Wang, J., Zheng, P., & Zhang, J. (2020). Big data analytics for cycle time related feature selection in the semiconductor wafer fabrication system. Computers & Industrial Engineering, 143, 106362. doi:10.1016/j.cie.2020.106362Neuts, M. F. (1967). A General Class of Bulk Queues with Poisson Input. The Annals of Mathematical Statistics, 38(3), 759-770. doi:10.1214/aoms/1177698869Deb, R. K., & Serfozo, R. F. (1973). Optimal control of batch service queues. Advances in Applied Probability, 5(2), 340-361. doi:10.2307/1426040Gurnani, H., Anupindi, R., & Akella, R. (1992). Control of batch processing systems in semiconductor wafer fabrication facilities. IEEE Transactions on Semiconductor Manufacturing, 5(4), 319-328. doi:10.1109/66.175364Avramidis, A. N., Healy, K. J., & Uzsoy, R. (1998). Control of a batch-processing machine: A computational approach. International Journal of Production Research, 36(11), 3167-3181. doi:10.1080/002075498192355Fowler, J. W., Phojanamongkolkij, N., Cochran, J. K., & Montgomery, D. C. (2002). Optimal batching in a wafer fabrication facility using a multiproduct G/G/c model with batch processing. International Journal of Production Research, 40(2), 275-292. doi:10.1080/00207540110081489Glassey, C. R., & Weng, W. W. (1991). Dynamic batching heuristic for simultaneous processing. IEEE Transactions on Semiconductor Manufacturing, 4(2), 77-82. doi:10.1109/66.79719Fowler, J. W., Phillips, D. T., & Hogg, G. L. (1992). Real-time control of multiproduct bulk-service semiconductor manufacturing processes. IEEE Transactions on Semiconductor Manufacturing, 5(2), 158-163. doi:10.1109/66.136278Sarin, S. C., Varadarajan, A., & Wang, L. (2010). A survey of dispatching rules for operational control in wafer fabrication. Production Planning & Control, 22(1), 4-24. doi:10.1080/09537287.2010.490014Koo, P.-H., & Moon, D. H. (2013). A Review on Control Strategies of Batch Processing Machines in Semiconductor Manufacturing. IFAC Proceedings Volumes, 46(9), 1690-1695. doi:10.3182/20130619-3-ru-3018.00203Leachman, R. C., Kang, J., & Lin, V. (2002). SLIM: Short Cycle Time and Low Inventory in Manufacturing at Samsung Electronics. Interfaces, 32(1), 61-77. doi:10.1287/inte.32.1.61.15ROBINSON, J. K., FOWLER, J. W., & BARD, J. F. (1995). The use of upstream and downstream information in scheduling semiconductor batch operations. International Journal of Production Research, 33(7), 1849-1869. doi:10.1080/00207549508904785NEALE, J. J., & DUENYAS, I. (2000). Control of manufacturing networks which contain a batch processing machine. IIE Transactions, 32(11), 1027-1041. doi:10.1080/07408170008967459SOLOMON, L., FOWLER, J. W., PFUND, M., & JENSEN, P. H. (2002). THE INCLUSION OF FUTURE ARRIVALS AND DOWNSTREAM SETUPS INTO WAFER FABRICATION BATCH PROCESSING DECISIONS. Journal of Electronics Manufacturing, 11(02), 149-159. doi:10.1142/s0960313102000370Çerekçi, A., & Banerjee, A. (2015). Effect of upstream re-sequencing in controlling cycle time performance of batch processors. Computers & Industrial Engineering, 88, 206-216. doi:10.1016/j.cie.2015.07.005Yeong-Dae, K., Dong-Ho, L., Jung-Ug, K., & Hwan-Kyun, R. (1998). A simulation study on lot release control, mask scheduling, and batch scheduling in semiconductor wafer fabrication facilities. Journal of Manufacturing Systems, 17(2), 107-117. doi:10.1016/s0278-6125(98)80024-1Bahaji, N., & Kuhl, M. E. (2008). A simulation study of new multi-objective composite dispatching rules, CONWIP, and push lot release in semiconductor fabrication. International Journal of Production Research, 46(14), 3801-3824. doi:10.1080/00207540600711879Li, Y., Jiang, Z., & Jia, W. (2013). An integrated release and dispatch policy for semiconductor wafer fabrication. International Journal of Production Research, 52(8), 2275-2292. doi:10.1080/00207543.2013.854938SPEARMAN, M. L., WOODRUFF, D. L., & HOPP, W. J. (1990). CONWIP: a pull alternative to kanban. International Journal of Production Research, 28(5), 879-894. doi:10.1080/00207549008942761Wein, L. M. (1988). Scheduling semiconductor wafer fabrication. IEEE Transactions on Semiconductor Manufacturing, 1(3), 115-130. doi:10.1109/66.4384Glassey, C. R., & Resende, M. G. C. (1988). Closed-loop job release control for VLSI circuit manufacturing. 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An Efficient Bi-objective Genetic Algorithm for the Single Batch-Processing Machine Scheduling Problem with Sequence Dependent Family Setup Time and Non-identical Job Sizes

This paper considers the problem of minimizing make-span and maximum tardiness simultaneously for scheduling jobs under non-identical job sizes, dynamic job arrivals, incompatible job families,and sequence-dependentfamily setup time on the single batch- processor, where split size of jobs is allowed between batches. At first, a new Mixed Integer Linear Programming (MILP) model is proposed for this problem; then, it is solved by -constraint method.Since this problem is NP-hard, a bi-objective genetic algorithm (BOGA) is offered for real-sized problems. The efficiency of the proposed BOGA is evaluated to be comparedwith many test problemsby -constraint method based on performance measures. The results show that the proposed BOGAis found to be more efficient and faster than the -constraint method in generating Pareto fronts in most cases

Dynamic Control for Batch Process Systems Using Stochastic Utility Evaluation

Most research studies in the batch process control problem are focused on optimizing system performance. The methods address the problem by minimizing single criterion such as cycle time and tardiness, or bi-criteria such as cycle time and tardiness, and earliness and tardiness. This research demonstrates the use of Stochastic Utility Evaluation (SUE) function approach to optimize system performance using multiple criteria. In long production cycles, the earliness and tardiness weight (utility) of products vary depending on the time. As the time approaches the due-date, it affects contractual penalties, loss of customer goodwill and the storage period for the completed products. It is necessary to reflect the weight of products for earliness and tardiness at decision epochs to decide on the optimal strategy. This research explores how stochastic utility function using stochastic information can be derived and used to strategically improve existing approaches for the batch process control problem. This research first explores how SUE function can be applied to existing model for bi-objective problem such as cycle time and tardiness. Benchmark strategies using SUE function (NACH-SUE, MBS-SUE, No idle and full batch) are compared to each other. The experimental results show that NACH-SUE effectively improves mean cycle time and tardiness performance respectively than other benchmark strategies. Next, SUE function for earliness and tardiness is used in an existing model to develop a tri-objective problem. Typically, this problem is very complex to solve due to its trade-off relationship. However SUE function makes it relatively easy to solve the tri-objective problem since SUE function can be incorporated in an existing model. It is observed that SUE function can be effectively used for solving a tri-objective problem. Performance improvement for averaged value of cycle time, earliness and tardiness is observed under a comprehensive set of experimental conditions

Dynamic Control of Serial-batch Processing Systems

This research explores how near-future information can be used to strategically control a batch processor in a serial-batch processor system setting. Specifically, improved control is attempted by using the upstream serial processor to provide near-future arrival information to the batch processor and further meet the re-sequencing requests to shorten critical products? arrival times to the batch processor. The objective of the research is to reduce mean cycle time and mean tardiness of the products being processed by the serial-batch processor system. This research first examines how mean cycle time performance of the batch processor can be improved by an upstream re-sequencing approach. A control strategy is developed by combining a look-ahead control approach with an upstream re-sequencing approach and is then compared with benchmark strategies through simulation. The experimental results indicate that the new control strategy effectively improves mean cycle time performance of the serial-batch processor system, especially when the number of product types is large and batch processor traffic intensity is low or medium. These conditions are often observed in typical semiconductor manufacturing environments. Next, the use of near-future information and an upstream re-sequencing approach is investigated for improving the mean tardiness performance of the serial-batch processor system. Two control strategies are devised and compared with the benchmark strategies through simulation. The experimental results show that the proposed control strategies improve the mean tardiness performance of the serial-batch processor system. Finally, the look-ahead control approaches that focus on mean cycle time and mean tardiness performances of the serial-batch processor system are embedded under a new control strategy that focuses on both performance measures simultaneously. It is demonstrated that look-ahead batching can be effectively used as a tool for controlling batch processors when multiple performance measures exist

A survey of scheduling problems with setup times or costs

Author name used in this publication: C. T. NgAuthor name used in this publication: T. C. E. Cheng2007-2008 > Academic research: refereed > Publication in refereed journalAccepted ManuscriptPublishe