Printed Receive Coils with High Acoustic Transparency for Magnetic Resonance Guided Focused Ultrasound.

In magnetic resonance guided focused ultrasound (MRgFUS) therapy sound waves are focused through the body to selectively ablate difficult to access lesions and tissues. A magnetic resonance imaging (MRI) scanner non-invasively tracks the temperature increase throughout the tissue to guide the therapy. In clinical MRI, tightly fitted hardware comprised of multichannel coil arrays are required to capture high quality images at high spatiotemporal resolution. Ablating tissue requires a clear path for acoustic energy to travel but current array materials scatter and attenuate acoustic energy. As a result coil arrays are placed outside of the transducer, clear of the beam path, compromising imaging speed, resolution, and temperature accuracy of the scan. Here we show that when coil arrays are fabricated by additive manufacturing (i.e., printing), they exhibit acoustic transparency as high as 89.5%. This allows the coils to be placed in the beam path increasing the image signal to noise ratio (SNR) five-fold in phantoms and volunteers. We also characterize printed coil materials properties over time when submerged in the water required for acoustic coupling. These arrays offer high SNR and acceleration capabilities, which can address current challenges in treating head and abdominal tumors allowing MRgFUS to give patients better outcomes

Active C4 electrodes for local field potential recording applications

Extracellular neural recording, with multi-electrode arrays (MEAs), is a powerful method used to study neural function at the network level. However, in a high density array, it can be costly and time consuming to integrate the active circuit with the expensive electrodes. In this paper, we present a 4 mm × 4 mm neural recording integrated circuit (IC) chip, utilizing IBM C4 bumps as recording electrodes, which enable a seamless active chip and electrode integration. The IC chip was designed and fabricated in a 0.13 μm BiCMOS process for both in vitro and in vivo applications. It has an input-referred noise of 4.6 μV rms for the bandwidth of 10 Hz to 10 kHz and a power dissipation of 11.25 mW at 2.5 V, or 43.9 μW per input channel. This prototype is scalable for implementing larger number and higher density electrode arrays. To validate the functionality of the chip, electrical testing results and acute in vivo recordings from a rat barrel cortex are presented.R01 NS072385 - NINDS NIH HHS; 1R01 NS072385 - NINDS NIH HH

Online and Offline BIST in IP-Core Design

This article presents an online and offline built-in self-test architecture implemented as an SRAM intellectual-property core for telecommunication applications. The architecture combines fault-latency reduction, code-based fault detection, and architecture-based fault avoidance to meet reliability constraint

Space programs summary no. 37-61, volume 1 for the period 1 November - 31 December 1969. Flight projects

Mariner Mars 1969 project, Mariner Mars 1971 project, and Viking 1973 project - research and advancement developmen

Minimizing Test Power in SRAM through Reduction of Pre-charge Activity

In this paper we analyze the test power of SRAM memories and demonstrate that the full functional pre-charge activity is not necessary during test mode because of the predictable addressing sequence. We exploit this observation in order to minimize power dissipation during test by eliminating the unnecessary power consumption associated with the pre-charge activity. This is achieved through a modified pre-charge control circuitry, exploiting the first degree of freedom of March tests, which allows choosing a specific addressing sequence. The efficiency of the proposed solution is validated through extensive Spice simulations

Testing Embedded Memories in Telecommunication Systems

Extensive system testing is mandatory nowadays to achieve high product quality. Telecommunication systems are particularly sensitive to such a requirement; to maintain market competitiveness, manufacturers need to combine reduced costs, shorter life cycles, advanced technologies, and high quality. Moreover, strict reliability constraints usually impose very low fault latencies and a high degree of fault detection for both permanent and transient faults. This article analyzes major problems related to testing complex telecommunication systems, with particular emphasis on their memory modules, often so critical from the reliability point of view. In particular, advanced BIST-based solutions are analyzed, and two significant industrial case studies presente