3 research outputs found
Design for pre-bond testability in 3D integrated circuits
In this dissertation we propose several DFT techniques specific to 3D
stacked IC systems. The goal has explicitly been to create techniques that
integrate easily with existing IC test systems. Specifically, this means
utilizing scan- and wrapper-based techniques, two foundations
of the digital IC test industry.
First, we describe a general test architecture for 3D ICs. In this
architecture, each tier of a 3D design is wrapped in test control logic that
both manages tier test
pre-bond and integrates the tier into the large test architecture post-bond.
We describe a new kind of boundary scan to provide the necessary test control
and observation of the partial circuits, and we propose
a new design methodology for test hardcore that ensures both pre-bond functionality
and post-bond optimality. We present the application of these techniques to
the 3D-MAPS test vehicle, which has proven their effectiveness.
Second, we extend these DFT techniques to circuit-partitioned designs. We find
that boundary scan design is generally sufficient, but that some 3D designs require
special DFT treatment. Most importantly, we demonstrate that the functional
partitioning inherent in 3D design can potentially decrease the total test cost
of verifying a circuit.
Third, we present a new CAD algorithm for designing 3D test wrappers. This algorithm
co-designs the pre-bond and post-bond wrappers to simultaneously minimize test
time and routing cost. On average, our algorithm utilizes over 90% of the wires
in both the pre-bond and post-bond wrappers.
Finally, we look at the 3D vias themselves to develop a low-cost, high-volume
pre-bond test methodology appropriate for production-level test. We describe
the shorting probes methodology, wherein large test probes are used to contact
multiple small 3D vias. This technique is an all-digital test method that
integrates seamlessly into existing test flows. Our
experimental results demonstrate two key facts: neither the large capacitance
of the probe tips nor the process variation in the 3D vias and the probe tips
significantly hinders the testability of the circuits.
Taken together, this body of work defines a complete test methodology for
testing 3D ICs pre-bond, eliminating one of the key hurdles to the
commercialization of 3D technology.PhDCommittee Chair: Lee, Hsien-Hsin; Committee Member: Bakir, Muhannad; Committee Member: Lim, Sung Kyu; Committee Member: Vuduc, Richard; Committee Member: Yalamanchili, Sudhaka
Communication synthesis of networks-on-chip (NoC)
The emergence of networks-on-chip (NoC) as the communication infrastructure solution
for complex multi-core SoCs presents communication synthesis challenges. This
dissertation addresses the design and run-time management aspects of communication
synthesis. Design reuse and the infeasibility of Intellectual Property (IP) core
interface redesign, requires the development of a Core-Network Interface (CNI) which
allows them to communicate over the on-chip network. The absence of intelligence
amongst the NoC components, entails the introduction of a CNI capable of not only
providing basic packetization and depacketization, but also other essential services
such as reliability, power management, reconguration and test support. A generic
CNI architecture providing these services for NoCs is proposed and evaluated in this
dissertation.
Rising on-chip communication power costs and reliability concerns due to these,
motivate the development of a peak power management technique that is both scalable
to dierent NoCs and adaptable to varying trac congurations. A scalable
and adaptable peak power management technique - SAPP - is proposed and demonstrated.
Latency and throughput improvements observed with SAPP demonstrate its
superiority over existing techniques.
Increasing design complexity make prediction of design lifetimes dicult. Post SoC deployment, an on-line health monitoring scheme, is essential to maintain con-
dence in the correct operation of on-chip cores. The rising design complexity and
IP core test costs makes non-concurrent testing of the IP cores infeasible. An on-line
scheme capable of managing IP core test in the presence of executing applications is
essential. Such a scheme ensures application performance and system power budgets
are eciently managed. This dissertation proposes Concurrent On-Line Test (COLT)
for NoC-based systems and demonstrates how a robust implementation of COLT using
a Test Infrastructure-IP (TI-IP) can be used to maintain condence in the correct
operation of the SoC
Explicit Building Block Multiobjective Evolutionary Computation: Methods and Applications
This dissertation presents principles, techniques, and performance of evolutionary computation optimization methods. Concentration is on concepts, design formulation, and prescription for multiobjective problem solving and explicit building block (BB) multiobjective evolutionary algorithms (MOEAs). Current state-of-the-art explicit BB MOEAs are addressed in the innovative design, execution, and testing of a new multiobjective explicit BB MOEA. Evolutionary computation concepts examined are algorithm convergence, population diversity and sizing, genotype and phenotype partitioning, archiving, BB concepts, parallel evolutionary algorithm (EA) models, robustness, visualization of evolutionary process, and performance in terms of effectiveness and efficiency. The main result of this research is the development of a more robust algorithm where MOEA concepts are implicitly employed. Testing shows that the new MOEA can be more effective and efficient than previous state-of-the-art explicit BB MOEAs for selected test suite multiobjective optimization problems (MOPs) and U.S. Air Force applications. Other contributions include the extension of explicit BB definitions to clarify the meanings for good single and multiobjective BBs. A new visualization technique is developed for viewing genotype, phenotype, and the evolutionary process in finding Pareto front vectors while tracking the size of the BBs. The visualization technique is the result of a BB tracing mechanism integrated into the new MOEA that enables one to determine the required BB sizes and assign an approximation epistasis level for solving a particular problem. The culmination of this research is explicit BB state-of-the-art MOEA technology based on the MOEA design, BB classifier type assessment, solution evolution visualization, and insight into MOEA test metric validation and usage as applied to test suite, deception, bioinformatics, unmanned vehicle flight pattern, and digital symbol set design MOPs