A Scalable Architecture for Coherence-Preserving Qubits

We propose scalable architectures for the coherence-preserving qubits introduced by Bacon, Brown, and Whaley [Phys. Rev. Lett. {\bf 87}, 247902 (2001)]. These architectures employ extra qubits providing additional degrees of freedom to the system. We show that these extra degrees of freedom can be used to counter errors in coupling strength within the coherence-preserving qubit and to combat interactions with environmental qubits. The presented architectures incorporate experimentally viable methods for inter-logical-qubit coupling and can implement a controlled phase gate via three simultaneous Heisenberg exchange operations. The extra qubits also provide flexibility in the arrangement of the physical qubits. Specifically, all physical qubits of a coherent-preserving qubit lattice can be placed in two spatial dimensions. Such an arrangement allows for universal cluster state computation.Comment: 4 pages, 4 figure

A Massively Scalable Architecture For Instant Messaging & Presence

This paper analyzes the scalability of Instant Messaging & Presence (IM&P) architectures. We take a queueing-based modelling and analysis approach to find the bottlenecks of the current IM&P architecture at the Dutch social network Hyves, as well as of alternative architectures. We use the Hierarchical Evaluation Tool (HIT) to create and analyse models analytically. Based on these results, we recommend a new architecture that provides better scalability than the current one. \u

A scalable architecture for quantum computation with molecular nanomagnets

A proposal for a magnetic quantum processor that consists of individual molecular spins coupled to superconducting coplanar resonators and transmission lines is carefully examined. We derive a simple magnetic quantum electrodynamics Hamiltonian to describe the underlying physics. It is shown that these hybrid devices can perform arbitrary operations on each spin qubit and induce tunable interactions between any pair of them. The combination of these two operations ensures that the processor can perform universal quantum computations. The feasibility of this proposal is critically discussed using the results of realistic calculations, based on parameters of existing devices and molecular qubits. These results show that the proposal is feasible, provided that molecules with sufficiently long coherence times can be developed and accurately integrated into specific areas of the device. This architecture has an enormous potential for scaling up quantum computation thanks to the microscopic nature of the individual constituents, the molecules, and the possibility of using their internal spin degrees of freedom.Comment: 27 pages, 6 figure

Long-range coupling and scalable architecture for superconducting flux qubits

Constructing a fault-tolerant quantum computer is a daunting task. Given any design, it is possible to determine the maximum error rate of each type of component that can be tolerated while still permitting arbitrarily large-scale quantum computation. It is an underappreciated fact that including an appropriately designed mechanism enabling long-range qubit coupling or transport substantially increases the maximum tolerable error rates of all components. With this thought in mind, we take the superconducting flux qubit coupling mechanism described in PRB 70, 140501 (2004) and extend it to allow approximately 500 MHz coupling of square flux qubits, 50 um a side, at a distance of up to several mm. This mechanism is then used as the basis of two scalable architectures for flux qubits taking into account crosstalk and fault-tolerant considerations such as permitting a universal set of logical gates, parallelism, measurement and initialization, and data mobility.Comment: 8 pages, 11 figure

Scalable Architecture for Distributed Video

As video applications become more important in organization’s communication, they require a new kind of architecture that meets the scalability requirements. Video applications are distributed in nature, and run almost exclusively over IP networks today. This paper investigates the architectural approaches for creating a scalable video network, and discusses the key potential bottlenecks in performance that the architecture has to address. Due to the limited size, the paper may not be able to cover scalable recording, streaming, firewall traversal, and integrations with scheduling and management applications. Since this content exists, the outstanding issues will be addresses during the presentation and in the Q&A session

Digital quantum simulators in a scalable architecture of hybrid spin-photon qubits

Resolving quantum many-body problems represents one of the greatest challenges in physics and physical chemistry, due to the prohibitively large computational resources that would be required by using classical computers. A solution has been foreseen by directly simulating the time evolution through sequences of quantum gates applied to arrays of qubits, i.e. by implementing a digital quantum simulator. Superconducting circuits and resonators are emerging as an extremely-promising platform for quantum computation architectures, but a digital quantum simulator proposal that is straightforwardly scalable, universal, and realizable with state-of-the-art technology is presently lacking. Here we propose a viable scheme to implement a universal quantum simulator with hybrid spin-photon qubits in an array of superconducting resonators, which is intrinsically scalable and allows for local control. As representative examples we consider the transverse-field Ising model, a spin-1 Hamiltonian, and the two-dimensional Hubbard model; for these, we numerically simulate the scheme by including the main sources of decoherence. In addition, we show how to circumvent the potentially harmful effects of inhomogeneous broadening of the spin systems

Scalable Architecture of MIMO Multi-carrier CDMA System on Programmable Logic

In this paper, a scalable architecture of the multicarrier CDMA system using Multiple-Input-Multiple-Output (MIMO) technology is designed in the programmable logic array. The system-level partitioning with different architecture design entries is described. The overall computing architecture for complex signal processing blocks, e.g., channel estimation, frequency domain equalization, demodulation etc is described. The MIMO architecture is easily extended from a SISO system with single antenna. This scalable architecture demonstrates resource utilization efficiency and easy extension to MIMO configurations