Hardware/Software Co-design for Particle Swarm Optimization Algorithm

[[abstract]]This paper presents a hardware/software (HW/SW) co-design approach using SOPC technique and pipeline design method to improve the performance of particle swarm optimization (PSO) for embedded applications. Based on modular design architecture, a particle updating accelerator module via hardware implementation for updating velocity and position of particles and a fitness evaluation module implemented on a soft-cored processor for evaluating the objective functions are respectively designed and work closely together to accelerate the evolution process. Thanks to a flexible design, the proposed approach can tackle various optimization problems of embedded applications without the need for hardware redesign. To compensate the deficiency in generating truly random numbers by hardware implementation, a particle re-initialization scheme is also presented in this paper to further improve the execution performance of the PSO. Experiment results have demonstrated that the proposed HW/SW co-design approach to realize PSO is capable of achieving a high-quality solution effectively.[[conferencetype]]國際[[conferencedate]]20101010~20101013[[iscallforpapers]]Y[[conferencelocation]]Istanbul, Turke

FPGA implementation of PSO algorithm and neural networks

This thesis describes the Field Programmable Gate Array (FPGA) implementations of two powerful techniques of Computational Intelligence (CI), the Particle Swarm Optimization algorithm (PSO) and the Neural Network (NN). Particle Swarm Optimization (PSO) is a popular population-based optimization algorithm. While PSO has been shown to perform well in a large variety of problems, PSO is typically implemented in software. Population-based optimization algorithms such as PSO are well suited for execution in parallel stages. This allows PSO to be implemented directly in hardware and achieve much faster execution times than possible in software. In this thesis, a pipelined architecture for hardware PSO implementation is presented. Benchmark functions solved by software and FPGA hardware PSO implementations are compared. NNs are inherently parallel, with each layer of neurons processing incoming data independently of each other. While general purpose processors have reached impressive processing speeds, they still cannot fully exploit this inherent parallelism due to their sequential architecture. In order to achieve the high neural network throughput needed for real-time applications, a custom hardware design is needed. In this thesis, a digital implementation of an NN is developed for FPGA implementation. The hardware PSO implementation is designed using only VHDL, while the NN hardware implementation is designed using Xilinx System Generator. Both designs are synthesized using Xilinx ISE and implemented on the Xilinx Virtex-II Pro FPGA Development Kit --Abstract, page iii

粒子群最適化法のネットワーク化による探索性能向上に関する研究

東京都市大学2017年度(平成29年