2 research outputs found
Ă–nellenĹ‘rzĂ©s Ă©s futásidejű verifikáciĂł számĂtĂłgĂ©pes programokban = Self-checking and run-time verification in computer programs
A kutatás eredmĂ©nye egy olyan, futásidejű hibadetektálásra alkalmas mĂłdszerkĂ©szlet kidolgozása számĂtĂłgĂ©pes programokhoz, amely formálisan megalapozott Ă©s illeszkedik a modell alapĂş tervezĂ©si folyamathoz. A futásidejű verifikáciĂł matematikai alapja egy általunk definiált, UML állapottĂ©rkĂ©pekhez illesztett temporális logikai nyelv (SC-LTL) valamint az ehhez kidolgozott gyors Ă©s kis erĹ‘forrásigĂ©nyű ellenĹ‘rzĂ©si algoritmus. Az ellenĹ‘rzĂ©st megvalĂłsĂtĂł forráskĂłd rĂ©szletek (assertions) generálására automatikus kĂłdgenerátort fejlesztettĂĽnk. A mĂłdszerkĂ©szlet alapján a futásidejű verifikáciĂł kĂ©t szinten vĂ©gezhetĹ‘ el: (1) A fejlesztĂ©s korai fázisaiban (a követelmĂ©nyanalĂzis után) a tervezĹ‘ a program biztonságos működĂ©sĂ©hez tartozĂł követelmĂ©nyeket formalizálja az SC-LTL temporális logika segĂtsĂ©gĂ©vel. Ezeket futásidĹ‘ben a programba illesztett kĂłdrĂ©szletek segĂtsĂ©gĂ©vel ellenĹ‘rizzĂĽk. ĂŤgy a kĂ©sĹ‘bbi fejlesztĂ©si fázisokban elĹ‘fordulĂł tervezĂ©si hibák következmĂ©nyei is kimutathatĂłk. (2) A fejlesztĂ©s elĹ‘rehaladtával rendelkezĂ©sre állĂł rĂ©szletes viselkedĂ©si modell mint referencia alapján törtĂ©nik a program állapot- Ă©s akciĂłszekvenciáinak teljes ellenĹ‘rzĂ©se, a modellbĹ‘l szintĂ©n automatikusan generált, futásidejű monitorozást biztosĂtĂł Ăşgynevezett watchdog kĂłd segĂtsĂ©gĂ©vel. Ennek cĂ©lja elsĹ‘sorban az implementáciĂłs hibák Ă©s a működĂ©si hibák (tranziens hardver hibák) felderĂtĂ©se. A hibadetektálás mĂłdszerkĂ©szletĂ©t kiegĂ©szĂtettĂĽk a hibakezelĂ©s modellezĂ©sĂ©re Ă©s verifikáciĂłjára szolgálĂł eljárásokkal. | The main result of the research is the elaboration of a set of methods that can be applied for the run-time verification of computer programs. These methods are formally proven and fit well to the model based software development process. The mathematical basis of run-time verification is our temporal logic language (SC-LTL) that is based on UML statechart diagrams, and the corresponding fast and low resource-demanding checker algorithm. To derive the assertions (i.e., the program code snippets that implement the checking), we have developed an automatic source code generator. On the basis of this set of methods, run-time checking of program execution is supported at two levels: (1) In the early phases of development the designer can formalize the program safety and liveness requirements using SC-LTL. These requirements are checked in run-time by the automatically generated assertions. This way design errors introduced in later design phases can also be detected. (2) The full checking of the state- and action sequences of program execution is based on a detailed design model constructed in the last development phases. The run-time monitoring is performed by a so-called watchdog code that is generated from the fully elaborated statechart model automatically. This is able to detect both implementation and operational errors. To complete the error detection framework, we proposed a statechart based method for the modeling and verification of run-time exception handling
Introduction to Runtime Verification
International audienceThe aim of this chapter is to act as a primer for those wanting to learn about Runtime Verification (RV). We start by providing an overview of the main specification languages used for RV. We then introduce the standard terminology necessary to describe the monitoring problem, covering the pragmatic issues of monitoring and instrumentation, and discussing extensively the monitorability problem