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Ring Amplifiers for Switched Capacitor Circuits
In this paper the fundamental concept of ring
amplification is introduced and explored. Ring amplifiers enable
efficient amplification in scaled environments, and possess the
benefits of efficient slew-based charging, rapid stabilization,
compression-immunity (inherent rail-to-rail output swing),
and performance that scales with process technology. A basic
operational theory is established, and the core benefits of this
technique are identified. Measured results from two separate
ring amplifier based pipelined ADCs are presented. The first
prototype IC, a simple 10.5-bit, 61.5dB SNDR pipelined ADC
which uses only ring amplifiers, is used to demonstrate the core
benefits. The second fabricated IC presented is a high-resolution
pipelined ADC which employs the technique of Split-CLS
to perform efficient, accurate amplification aided by ring
amplifiers. The 15-bit ADC is implemented in a 0.18 ÎĽm CMOS
technology and achieves 76.8 dB SNDR and 95.4 dB SFDR
at 20 Msps while consuming 5.1 mW, achieving a FoM of
45 fJ/conversion-step.Keywords: correlated level shifting,
analog to digital conversion,
analog to digital converter,
slew-based,
RAMP,
rail-to-rail,
ring amplification,
ADC,
CLS,
ringamp,
A/D,
low power,
ring amp,
scaling,
Split-CLS,
ring amplifier,
high resolution,
switched-capacitor,
scalability,
stabilized ring oscillator,
nanoscale CMOSThis is the author's peer-reviewed final manuscript, as accepted by the publisher. The published article is copyrighted by IEEE-Institute of Electrical and Electronics Engineers and can be found at: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=4. ©2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works
Noise and thermal stability of vibrating micro-gyrometers preamplifiers
The preamplifier is a critical component of gyrometer's electronics. Indeed
the resolution of the sensor is limited by its signal to noise ratio, and the
gyrometer's thermal stability is limited by its gain drift. In this paper, five
different kinds of preamplifiers are presented and compared. Finally, the
design of an integrated preamplifier is shown in order to increase the gain
stability while reducing its noise and size.Comment: Submitted on behalf of EDA Publishing Association
(http://irevues.inist.fr/EDA-Publishing
Design of a tunable multi-band differential LC VCO using 0.35 mu m SiGe BiCMOS technology for multi-standard wireless communication systems
In this paper, an integrated 2.2-5.7GHz multi-band differential LC VCO for multi-standard wireless communication systems was designed utilizing 0.35 mu m SiGe BiCMOS technology. The topology, which combines the switching inductors and capacitors together in the same circuit, is a novel approach for wideband VCOs. Based on the post-layout simulation results, the VCO can be tuned using a DC voltage of 0 to 3.3 V for 5 different frequency bands (2.27-2.51 GHz, 2.48-2.78 GHz, 3.22-3.53 GHz, 3.48-3.91 GHz and 4.528-5.7 GHz) with a maximum bandwidth of 1.36 GHz and a minimum bandwidth of 300 MHz. The designed and simulated VCO can generate a differential output power between 0.992 and -6.087 dBm with an average power consumption of 44.21 mW including the buffers. The average second and third harmonics level were obtained as -37.21 and -47.6 dBm, respectively. The phase noise between -110.45 and -122.5 dBc/Hz, that was simulated at 1 MHz offset, can be obtained through the frequency of interest. Additionally, the figure of merit (FOM), that includes all important parameters such as the phase noise, the power consumption and the ratio of the operating frequency to the offset frequency, is between -176.48 and -181.16 and comparable or better than the ones with the other current VCOs. The main advantage of this study in comparison with the other VCOs, is covering 5 frequency bands starting from 2.27 up to 5.76 GHz without FOM and area abandonment. Output power of the fundamental frequency changes between -6.087 and 0.992 dBm, depending on the bias conditions (operating bands). Based on the post-layout simulation results, the core VCO circuit draws a current between 2.4-6.3 mA and between 11.4 and 15.3 mA with the buffer circuit from 3.3 V supply. The circuit occupies an area of 1.477 mm(2) on Si substrate, including DC, digital and RF pads
The 30-GHz monolithic receive module
The fourth year progress is described on a program to develop a 27.5 to 30 GHz GaAs monolithic receive module for spaceborne-communication antenna feed array applications, and to deliver submodules for experimental evaluation. Program goals include an overall receive module noise figure of 5 dB, a 30 dB RF to IF gain with six levels of intermediate gain control, a five bit phase shifter, and a maximum power consumption of 250 mW. Submicron gate length single and dual gate FETs are described and applied in the development of monolithic gain control amplifiers and low noise amplifiers. A two-stage monolithic gain control amplifier based on ion implanted dual gate MESFETs was designed and fabricated. The gain control amplifier has a gain of 12 dB at 29 GHz with a gain control range of over 13 dB. A two-stage monolithic low noise amplifier based on ion implanted MESFETs which provides 7 dB gain with 6.2 dB noise figure at 29 GHz was also developed. An interconnected receive module containing LNA, gain control, and phase shifter submodules was built using the LNA and gain control ICs as well as a monolithic phase shifter developed previously under this program. The design, fabrication, and evaluation of this interconnected receiver is presented. Progress in the development of an RF/IF submodule containing a unique ion implanted diode mixer diode and a broadband balanced mixer monolithic IC with on-chip IF amplifier and the initial design of circuits for the RF portion of a two submodule receiver are also discussed
Reducing MOSFET 1/f Noise and Power Consumption by "Switched Biasing"
Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in electronic circuits, whereas the switched biasing technique reduces the 1/f noise itself. Whereas noise reduction techniques generally lead to more power consumption, switched biasing can reduce the power consumption. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its intrinsic 1/f noise. As the 1/f noise is reduced at its physical roots, high frequency circuits, in which 1/f noise is being upconverted, can also benefit. This is demonstrated by applying switched biasing in a 0.8 Âżm CMOS sawtooth oscillator. By periodically switching off the bias currents, during time intervals that they are not contributing to the circuit operation, a reduction of the 1/f noise induced phase noise by more than 8 dB is achieved, while the power consumption is also reduced by 30
Design of Inverter Based CMOS Amplifiers in Deep Nanoscale Technologies
In this work, it is proposed a fully differential ring amplifier topology with a deadzone
voltage created by a CMOS resistor with a biasing circuit to increase the robustness over PVT
variations.
The study focuses on analyzing the performance of the ring amplifier over process,
temperature, and supply voltage variations, in order to guarantee a viable industrial employment
in a 7 nm FinFET CMOS technology node for being used as residue amplifier in ADCs.
A ring amplifier is a small modular amplifier, derived from a ring oscillator. It is simple
enough that it can quickly be designed using only a few inverters, capacitors, and switches. It can
amplify with rail-to-rail output swing, competently charge large capacitive loads using slew-based
charging, and scale well in performance according to process trends.
In typical process corner, a gain of 72 dB is achieved with a settling time of 150 ps.
Throughout the study, the proposed topology is compared with others presented in literature
showing better results over corners and presenting a faster response. The proposed topology isn’t
yet suitable for industry use, because it presents one corner significantly slower than the rest,
namely process corner FF 125 °C, and process corner FS -40 °C with a small oscillation
throughout the entire amplification period.
Nevertheless, it proved itself to be a promising technique, showing a high gain and a fast
settling without oscillation phase, with room for improvement.Neste trabalho, Ă© proposta uma topologia de ring amplifier com a deadzone a ser criada
através de uma resistência CMOS com um circuito de polarização para aumentar a robustez para
as variações PVT.
O estudo foca-se em analisar a performance do ring amplifier nas variações de processo,
temperatura e tensão de alimentação, de forma a garantir um uso viável em indústria na tecnologia
de 7 nm FinFET CMOS, para ser usado como amplificador de resĂduo em ADCs.
Um ring amplifier é um pequeno amplificador modular, derivado do ring oscillator. É
simples o suficiente para ser facilmente projetado usando apenas poucos inversores,
condensadores e interruptores. Consegue amplificar com rail-to-rail output swing, carregar
grandes cargas capacitivas com carregamento slew-based e escalar bem em termos de
performance de acordo com o processo.
No typical process corner, foi obtido um ganho de 72 dB com um tempo de estabilização
de 150 ps. Durante o estudo, a topologia proposta Ă© comparada com outras presentes na literatura
mostrando melhores resultados over corners e apresentando uma resposta mais rápida. A
topologia proposta ainda não está preparada para uso industrial uma vez que apresenta um corner
significativamente mais lento que os restantes, nomeadamente, process corner FF 125 °C, e outro
process corner, FS -40 °C, com uma pequena oscilação durante todo o perĂodo de amplificação.
Todavia, provou ser uma técnica promissora, apresentando um ganho elevado e uma rápida
estabilização sem fase de oscilação, com espaço para melhoria
Low-Power Slew-Rate Boosting Based 12-Bit Pipeline ADC Utilizing Forecasting Technique in the Sub-ADCS
The dissertation presents architecture and circuit solutions to improve the power efficiency of high-speed 12-bit pipelined ADCs in advanced CMOS technologies. First, the 4.5bit algorithmic pipelined front-end stage is proposed. It is shown that the algorithmic pipelined ADC requires a simpler sub-ADC and shows lower sensitivity to the Multiplying DAC (MDAC) errors and smaller area and power dissipation in comparison to the conventional multi-bit per stage pipelined ADC. Also, it is shown that the algorithmic pipelined architecture is more tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture. To take full advantage of these properties, a modified residue curve for the pipelined ADC is proposed. This concept introduces better linearity compared with the conventional residue curve of the pipelined ADC; this approach is particularly attractive for the digitization of signals with large peak to average ratio such as OFDM coded signals. Moreover, the minimum total required transconductance for the different architectures of the 12-bit pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. By employing this calculation, the most power efficient architecture for realizing the 12-bit pipelined ADC is selected. Then, a technique for slew-rate (SR) boosting in switched-capacitor circuits is proposed in the order to be utilized in the proposed 12-bit pipelined ADC. This technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high slew-rate is demanded by large input signal. The proposed architecture employs simple circuitry to detect the need of injecting current at the output load by implementing a Pre-Amp followed by a class-B amplifier, embedded with a pre-defined hysteresis, in parallel with the main amplifier to boost its slew phase. The proposed solution requires small static power since it does not need high dc-current at the output stage of the main amplifier. The proposed technique is suitable for high-speed low-power multi-bit/stage pipelined ADC applications. Both transistor-level simulations and experimental results in TSMC 40nm technology reduces the slew-time for more than 45% and shorts the 1% settling time by 28% when used in a 4.5bit/stage pipelined ADC; power consumption increases by 20%. In addition, the technique of inactivating and disconnecting of the sub-ADC’s comparators by forecasting the sign of the sampled input voltage is proposed in the order to reduce the dynamic power consumption of the sub-ADCs in the proposed 12-bit pipelined ADC. This technique reduces the total dynamic power consumption more than 46%. The implemented 12-bit pipelined ADC achieves an SNDR/SFDR of 65.9/82.3 dB at low input frequencies and a 64.1/75.5 dB near Nyquist frequency while running at 500 MS/s. The pipelined ADC prototype occupies an active area of 0.9 mm^2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively
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