162 research outputs found
Quantum Cellular Automata
Quantum cellular automata (QCA) are reviewed, including early and more recent
proposals. QCA are a generalization of (classical) cellular automata (CA) and
in particular of reversible CA. The latter are reviewed shortly. An overview is
given over early attempts by various authors to define one-dimensional QCA.
These turned out to have serious shortcomings which are discussed as well.
Various proposals subsequently put forward by a number of authors for a general
definition of one- and higher-dimensional QCA are reviewed and their properties
such as universality and reversibility are discussed.Comment: 12 pages, 3 figures. To appear in the Springer Encyclopedia of
Complexity and Systems Scienc
Novel ultra-energy-efficient reversible designs of sequential logic quantum-dot cellular automata flip-flop circuits
The version of record of this article, first published in [The Journal of Supercomputing], is available online at Publisher’s website: http://dx.doi.org/10.1007/s11227-023-05134-1Quantum-dot cellular automata (QCA) is a technological approach to implement digital circuits with exceptionally high integration density, high switching frequency, and low energy dissipation. QCA circuits are a potential solution to the energy dissipation issues created by shrinking microprocessors with ultra-high integration densities. Current QCA circuit designs are irreversible, yet reversible circuits are known to increase energy efficiency. Thus, the development of reversible QCA circuits will further reduce energy dissipation. This paper presents novel reversible and irreversible sequential QCA set/reset (SR), data (D), Jack Kilby (JK), and toggle (T) flip-flop designs based on the majority gate that utilizes the universal, standard, and efficient (USE) clocking scheme, which allows the implementation of feedback paths and easy routing for sequential QCA-based circuits. The simulation results confirm that the proposed reversible QCA USE sequential flip-flop circuits exhibit energy dissipation less than the Landauer energy limit. Irreversible QCA USE flip-flop designs, although having higher energy dissipation, sometimes have floorplan areas and delay times less than those of reversible designs; therefore, they are also explored. The trade-offs between the energy dissipation versus the area cost and delay time for the reversible and irreversible QCA circuits are examined comprehensively
New Symmetric and Planar Designs of Reversible Full-Adders/Subtractors in Quantum-Dot Cellular Automata
Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies,
promising alternative to CMOS technology due to faster speed, smaller size,
lower power consumption, higher scale integration and higher switching
frequency. Also, power dissipation is the main limitation of all the nano
electronics design techniques including the QCA. Researchers have proposed the
various mechanisms to limit this problem. Among them, reversible computing is
considered as the reliable solution to lower the power dissipation. On the
other hand, adders are fundamental circuits for most digital systems. In this
paper, Innovation is divided to three sections. In the first section, a method
for converting irreversible functions to a reversible one is presented. This
method has advantages such as: converting of irreversible functions to
reversible one directly and as optimal. So, in this method, sub-optimal methods
of using of conventional reversible blocks such as Toffoli and Fredkin are not
used, having of minimum number of garbage outputs and so on. Then, Using the
method, two new symmetric and planar designs of reversible full-adders are
presented. In the second section, a new symmetric, planar and fault tolerant
five-input majority gate is proposed. Based on the designed gate, a reversible
full-adder are presented. Also, for this gate, a fault-tolerant analysis is
proposed. And in the third section, three new 8-bit reversible
full-adder/subtractors are designed based on full-adders/subtractors proposed
in the second section. The results are indicative of the outperformance of the
proposed designs in comparison to the best available ones in terms of area,
complexity, delay, reversible/irreversible layout, and also in logic level in
terms of garbage outputs, control inputs, number of majority and NOT gates
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