Modeling of thermally induced skew variations in clock distribution network

Clock distribution network is sensitive to large thermal gradients on the die as the performance of both clock buffers and interconnects are affected by temperature. A robust clock network design relies on the accurate analysis of clock skew subject to temperature variations. In this work, we address the problem of thermally induced clock skew modeling in nanometer CMOS technologies. The complex thermal behavior of both buffers and interconnects are taken into account. In addition, our characterization of the temperature effect on buffers and interconnects provides valuable insight to designers about the potential impact of thermal variations on clock networks. The use of industrial standard data format in the interface allows our tool to be easily integrated into existing design flow

Análisis de temperatura en FPGAs

Este proyecto se ha basado fundamentalmente en el diseño, desarrollo y caracterización de osciladores anillo en una FPGA, modelo Virtex-5 para obtener la temperatura de la misma a través de la frecuencia de oscilación de los sensores. Para ello primero se diseñaron los osciladores anillo en VHDL y una lógica de control que permitiera obtener la frecuencia de oscilación y controlase la habilitación/deshabilitación de los sensores. Los datos de la frecuencia obtenidos fueron enviados a través de la interfaz RS232 (UART) al ordenador. Con el fin de almacenar y procesar esos datos se crea una interfaz en Matlab. Tras obtener los datos se realizaron distintas representaciones gráficas para ayudar a la interpretación de los resultados. Con el fin de obtener la temperatura de la placa y poder así realizar la calibración de los sensores anillo, se monitorizó el diodo interno de temperatura pre-calibrado que posee el modelo de FPGA utilizado. Por tal razón, el módulo System Monitor tuvo que ser considerado como parte de nuestro diseño obteniendo aproximadamente la temperatura del FPGA como su respectivo voltaje de núcleo Una vez definido el oscilador e interconectarlo con Matlab, se procedió a realizar tres experimentos diferentes: El primero consistió en identificar el número de inversores que son necesarios para que los datos recogidos del sensor anillo sean los más fieles posibles a la realidad. En el segundo se realizó la calibración de dos sensores próximos al diodo calibrado interno que posee el FPGA para estudiar cual es la variación de la frecuencia de oscilación con respecto el voltaje de núcleo, la temperatura y la posición de los anillos. Y el tercero consistió en colocar 48 sensores distribuidos por toda la FPGA y obtener la frecuencia de oscilación de cada uno de ellos, procesando un número determinado de muestras por cada sensor. En resumen, se han realizado 12 versiones de circuitos sobre los cuales se han hecho 21.504 medidas. Y el código contiene unas 8.700 líneas divididas en 6 ficheros diferentes.The aim of this project tackles the design, development and analysis of ring oscillators, which comprises of a series of inverters, implemented over an FPGA-Virtex-5 in order to sense the temperature gradient of hot-spots in FPGAs. Therefore, our proposal consists of designing an array of ring oscillators which are monitored by a control central unit which actives the period required to conduct several stages of our design in order to read the counter generated by ring oscillator. The data obtained are computationally processed carrying out varies operations such as frequency oscillation calculation, median and standard deviation as well as several graphs depicting profiles thermal. Likewise, a PC connected via UART to the FPGA in charges of receiving the data from our design. In order to get the absolute temperature of the tested FPGA and be able to perform calibration of the sensor ring the System Monitor module was used. It’s worth mentioning that this Xilinx FPGA contains a pre-calibrated built-in thermal diode which is sensed by the module indicated earlier. Several experiments were carried out evaluating the ring oscillator design. It can be mentioned the following: As a first experiment, it was examined the number of inverters utilized in each sensor by means of several design combinations and evaluated their respective sensor performance. As second one, it was calibrated two ring oscillator sensors closets to the position of the built-in thermal diode in order to evaluate the variation of the tuned frequency related to absolute temperature, voltage core and relative placement within FPGA. Lastly, it was tested the frequency oscillation of each sensor considering an array of 48 thermal sensors distributed properly over the FPGA. In summary, there have been made 12 circuit versions and 21.504 measurements. And the code contains 8.700 lines divided into 6 different files

Mise en oeuvre de l'aspect démonstrateur des transistors mono-électroniques

Depuis 1965, la loi de Moore, loi de doublement du nombre de transistors dans une puce tous les deux ans, n’a jamais été contredite. II faut attendre septembre 2007 pour que son inventeur lui-même, Gordon Moore, ne la considère plus valide et estime sa fin dans les dix à quinze ans à venir. Le problème des limites physiques de la technologie CMOS actuelle est alors aujourd’hui posé : jusqu’où la miniaturisation peut-elle continuer? Combien d'atomes faut-il pour faire un transistor fonctionnel ? Y a-t-il d'autres matériaux que les semiconducteurs qui permettraient d'aller au delà des limites physiques, ou encore d'autres moyens de coder l'information de façon plus efficace? La technologie des transistors à un électron (SET, Single Electron Transistor) est une des solutions possible et semble très prometteuse. Bien souvent cantonné à un fonctionnement bien en dessous de la température ambiante, les premiers SETs métalliques démontrant un caractère typique de blocage de Coulomb à des températures dépassant 130 °C sont une des premières réussites du projet "SEDIMOS" ici à l'Université de Sherbrooke. Véritable couteau-suisse, le SET présente des caractéristiques électriques qui vont au delà de la technologie CMOS actuelle tout en pouvant copier cette dernière sans grande difficulté. Dans un circuit, il faut cependant lui adressé [i.e. adresser] certains problèmes tel [i.e. tels] qu’un faible courant de commande, un faible gain en tension et un délai important. Mais tous ces aléas peuvent être cependant contournés ou réduits par une conception adaptée de ces circuits. Cependant, il existe une difficulté à fabriquer de multiples SETs ayant des caractéristiques électriques similaires. En outre, les circuits peuvent exiger des SETs avec un haut niveau de performance. Souhaitant repousser les limites actuelles de la logique SET, le but de cette maîtrise est de réaliser un inverseur SET développant principalement les deux caractéristiques critiques mentionnées dans le paragraphe précédent. Sous un travail à température ambiante, voir supérieur, l'inverseur devra développer un gain en tension supérieur à l'unité. Les SET métalliques présentés dans ce travail sont fabriqués sur un substrat de silicium oxydé par oxydation sèche. Le procédé de fabrication utilisé est cependant compatible avec l'unité de fabrication finale du CMOS, Back End of Line (BEOL). Un coût réduit, un faible bilan thermique, et une amélioration de la densité d'intégration dans le cadre d'une production de masse de circuits hautement intégrés rendent ce procédé de fabrication très attrayant. L'objectif principal de cette maîtrise peut être divisé en 3 parties : (1) L'étude des paramètres électriques tels que les tension, gain, capacité d'attaque et puissance du circuit inverseur SET, (2) l'amélioration des performances de la logique SET grâce à la modification des paramètres physiques des SETs et de l'architecture de leurs circuits et (3) la présentation des résultats de mesures électriques

Parametric Yield of VLSI Systems under Variability: Analysis and Design Solutions

Variability has become one of the vital challenges that the designers of integrated circuits encounter. variability becomes increasingly important. Imperfect manufacturing process manifest itself as variations in the design parameters. These variations and those in the operating environment of VLSI circuits result in unexpected changes in the timing, power, and reliability of the circuits. With scaling transistor dimensions, process and environmental variations become significantly important in the modern VLSI design. A smaller feature size means that the physical characteristics of a device are more prone to these unaccounted-for changes. To achieve a robust design, the random and systematic fluctuations in the manufacturing process and the variations in the environmental parameters should be analyzed and the impact on the parametric yield should be addressed. This thesis studies the challenges and comprises solutions for designing robust VLSI systems in the presence of variations. Initially, to get some insight into the system design under variability, the parametric yield is examined for a small circuit. Understanding the impact of variations on the yield at the circuit level is vital to accurately estimate and optimize the yield at the system granularity. Motivated by the observations and results, found at the circuit level, statistical analyses are performed, and solutions are proposed, at the system level of abstraction, to reduce the impact of the variations and increase the parametric yield. At the circuit level, the impact of the supply and threshold voltage variations on the parametric yield is discussed. Here, a design centering methodology is proposed to maximize the parametric yield and optimize the power-performance trade-off under variations. In addition, the scaling trend in the yield loss is studied. Also, some considerations for design centering in the current and future CMOS technologies are explored. The investigation, at the circuit level, suggests that the operating temperature significantly affects the parametric yield. In addition, the yield is very sensitive to the magnitude of the variations in supply and threshold voltage. Therefore, the spatial variations in process and environmental variations make it necessary to analyze the yield at a higher granularity. Here, temperature and voltage variations are mapped across the chip to accurately estimate the yield loss at the system level. At the system level, initially the impact of process-induced temperature variations on the power grid design is analyzed. Also, an efficient verification method is provided that ensures the robustness of the power grid in the presence of variations. Then, a statistical analysis of the timing yield is conducted, by taking into account both the process and environmental variations. By considering the statistical profile of the temperature and supply voltage, the process variations are mapped to the delay variations across a die. This ensures an accurate estimation of the timing yield. In addition, a method is proposed to accurately estimate the power yield considering process-induced temperature and supply voltage variations. This helps check the robustness of the circuits early in the design process. Lastly, design solutions are presented to reduce the power consumption and increase the timing yield under the variations. In the first solution, a guideline for floorplaning optimization in the presence of temperature variations is offered. Non-uniformity in the thermal profiles of integrated circuits is an issue that impacts the parametric yield and threatens chip reliability. Therefore, the correlation between the total power consumption and the temperature variations across a chip is examined. As a result, floorplanning guidelines are proposed that uses the correlation to efficiently optimize the chip's total power and takes into account the thermal uniformity. The second design solution provides an optimization methodology for assigning the power supply pads across the chip for maximizing the timing yield. A mixed-integer nonlinear programming (MINLP) optimization problem, subject to voltage drop and current constraint, is efficiently solved to find the optimum number and location of the pads